mjh5363@psu.edu

Using MultiSIM PLD Design with BASYS2

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Does anyone use MultiSIM to program BASYS2? I teach an intro digital course that uses MultiSIM PLD Design to schematically program BASYS2 fpgas. I get a message when using ADEPT to upload that states: "Startup clock for this file is 'CCLK' instead of 'JTAG CLK.' Problems will likely occur. Associate config file with device anyway?" I can change this in Xilinx, but can't seem to in MultiSIM PLD. Any thoughts?

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