Matrix reception module in vhdl

[cristian_zanetti]

Good morning, I am currently using the uart protocol to communicate my Nexys 4 DDR with Matlab, but I have the inconvenience that I need to send signals of more than 8 bits, someone knows how to receive matrices in vhdl by uart (something like the function fread de matlab).

 

Thank you for your attention

[D@n]

@cristian_zanetti,

Is this the sort of thing you are looking for?  Something with a host interface that looks something like this in C++?

I put a series of articles together discussing how to build it.  While the code is all in Verilog, the articles break it down far enough that, in my most humble of opinions, you should be able to rebuild the interface in VHDL should you wish to do so.

Let me know,

Dan

[cristian_zanetti]

What I want is to send a matrix to the FPGA and the FPGA to read it. How can I store or receive this data in the FPGA, since these come in an 8-bit package ?.
I wish to have a fread in vhdl as would be done in MATLAB if I make myself understood

[D@n]

@cristian_zanetti,

The link(s) above shows you how to build an readi function that you can use to read from the FPGA just like a memcpy, and an fwritei that you can use to write to your FPGA just like a memcpy.  Both are very similar to an fread().

Dan