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Nexys Video HDMI Capabilities




I'm trying to understand the HDMI capabilities of the Nexys Video Artix-7.

I don't own a board yet, so these queries are based on reading spec sheets; please excuse any errors or omissions on my part.

The FPGA on the Nexys Video is XC7A200T-1SBG484C, which supports 4 GTP transceivers at 3.75 Gbit/s [1]. However, based on my best interpretation of the Nexys Video data sheet [2] the HDMI ports aren't using the GTP transceivers. The GTPs are used for DisplayPort and FMC connector. 

Given the HDMI ports aren't using the GTPs, what is the maximum data rate the FPGA can support for them?

The HDMI input has an Analog AD8195 buffer, which supports 2.25 Gbps data rate [3].
The HDMI output has a TI TMDS141 buffer, which also supports a 2.25 Gbps data rate [4].

This seems to limit the Nexys to 720p60 or 1080p30, whatever the FPGA may be capable of. Though if these rates are per TDMS channel then that's plenty for 1080p60.
However, in the Digilent HDMI demo a video format of 1080p60 is shown [5].

In summary, can someone clarify what video formats and data rates the Nexys Video is capable of on HDMI input and output?

Thanks in advance,

For reference the data rate of some common HDMI formats: 

  • 720p60 -  1.45 Gbit/s (HDMI 1.0+)
  • 1080p30 -  1.58 Gbit/s (HDMI 1.0+)
  • 1080p60 -  3.20 Gbit/s (HDMI 1.0+)
  • 2160p30 -  6.18 Gbit/s (HDMI 1.4+)
  • 2160p60 - 12.54 Gbit/s (HDMI 2.0+)

[1] https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf (page 50)
[2] https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexysvideo_rm.pdf
[3] http://www.analog.com/en/products/audio-video/hdmidvi-transmitters/ad8195.html
[4] http://www.ti.com/product/tmds141
[5] https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-hdmi-demo/start

Edited by Flux
Added possibly different interpretation of buffer chip bandwidth.
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18 minutes ago, [email protected] said:


I have 1080p60 working on my desktop using the Nexys Video, both transmit and receive.  The limitation I'm running into so far isn't a video rate bottleneck, but rather a memory bandwidth bottleneck.


@[email protected] thanks for the confirmation that 1080p60 HDMI is possible on input and output. I'm intrigued to know how the board managing 3.2 Gbit/second for 1080p60 HDMI without using the GTPs.

If I'm reading the memory spec correctly, then theoretical bandwidth is 12.8 Gbit/second. Is that not enough for 1080p60 with capacity to spare for processing?  


Edited by Flux
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I'm going to violate the "never do math in public" rule here, but let's see if I can get this right:

  1. A 1080p60 video stream contains 8'bits per pixel for 3 pixels for a total of 24 bits.  In order to facilitate further processing, we'll store this in 32-bits.  Further, there are 1920x1080 pixels per frame, and 60 frames per second, so storing this information requires storing 32'bits * 1920 * 1080 * 60 Hz or 3.98 Gbps.
  2. Reading this information to display it would also require the same bandwidth, or another 3.98 Gbps from memory.
  3. The Nexys Video memory can handle eight 16-bit transactions per 100MHz clock, or 12.8Gbps.  There's a lot of latency involved, though ... on the order of 24 clocks (I can't remember the exact number--Xilinx messed up on the performance of their MIG controller).  You also have to account for the system taking the SDRAM down for maintenance, so figure you can get about 12Gbps or so.

That means that two 1080p60 data streams, one going to memory and one coming from memory, will consume 66% of your memory bandwidth.  If you choose to fracture those transactions by having a CPU work on them via some sort of random access, you could easily and quickly consume the last of this bandwidth.

My point is simply this: think through your entire design as you plan it out.  As with any FPGA design, the devil lurks in the details.



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