Ovidiu Posted November 15, 2017 Share Posted November 15, 2017 Hello experts! I have an Arty Z7-20. For school projects I have to learn VHDL for FPGA programming, only for FPGA applications. What should I do to disable (inhibit) PS and to safely use PL only? Link to comment Share on other sites More sharing options...
jpeyron Posted November 15, 2017 Share Posted November 15, 2017 Hi @Ovidiu, The Arty-Z7-20 has a ZYNQ processor. You can design projects without using the ZYNQ processor in VHDL depending on the components you are trying to interact with. There is no disable process that i am aware of. Some of the components on the Arty-Z7-20 are tied directly to the ZYNQ processor and can only be used by the PS like the usb uart and the Ethernet. What type of projects are you trying to do? thank you, Jon Link to comment Share on other sites More sharing options...
Ovidiu Posted November 15, 2017 Author Share Posted November 15, 2017 Hi Jon, I have to do simple projects like adders, registers, multipliers etc. "PS7_stub.vhd" (find on Google search) could do the job I asked? Link to comment Share on other sites More sharing options...
jpeyron Posted November 15, 2017 Share Posted November 15, 2017 Hi @Ovidiu, Is this here the file you are referring to? I am not sure what this VHDL code accomplishes. I can ask more experience engineers what this code does. If you are making adders, register, multipliers in hdl this should not be an issue with the zynq processor as long as you are not trying to use components directly connected to the Zynq processor like the usb uart. Here is an XADC demo in Verilog that does not use the zynq processor. cheers, Jon Link to comment Share on other sites More sharing options...
Ovidiu Posted November 15, 2017 Author Share Posted November 15, 2017 Hi Jon So, I shall ignore the PS. Yes, that is the file. I spent a week trying to understand if I need it. Please tell me if you find out. Link to comment Share on other sites More sharing options...
BogdanVanca Posted November 16, 2017 Share Posted November 16, 2017 Hi @Ovidiu, As @jpeyron said, in Vivado doesn't exist a disable process to inhibit the Processing System or even the PLL. If you chose for example to make a simple adder without using PS, you only need to create a new Vivado Project in which you instantiate your HDL components. That's all. You can even create your own UART HDL controller, keeping everything away from PS by writing everything in HDL code. But this is far away from a simple school project. So, my response to your first question is it that you can create adders, registers or multipliers on Arty Z-7. The file that you linked to, does a couple of instantiations for the PS. But you don't need to take care of that, all the instantiations can be done using a graphic interface or a presets file. But this is in case if you want to use the PS, if you are not using it, you don't need all this presets. If you have any other questions please feel free to ask. cheers, Bogdan Link to comment Share on other sites More sharing options...
Ovidiu Posted November 16, 2017 Author Share Posted November 16, 2017 Multumesc Bogdan, Thank you, now it's cristal clear. No more worries, I am happy now! Link to comment Share on other sites More sharing options...
salonishirodkar Posted December 29, 2017 Share Posted December 29, 2017 Since the FPGA on the Z7 has more resources than the one on the original Arty, you may have to do some tweaking on things like the device number. I would not expect the RTL or pre-configured bit file to run straight off the shelf. Link to comment Share on other sites More sharing options...
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Ovidiu
Hello experts!
I have an Arty Z7-20. For school projects I have to learn VHDL for FPGA programming, only for FPGA applications.
What should I do to disable (inhibit) PS and to safely use PL only?
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