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techno-rogue

How high is the switching rate of the High-Speed PMOD on the Zybo Board?

Question

I use a 10MHz clock and a 2-bit register to generate a 100 ns pulse at a frequency of 2.5 MHz(100 ns on, 300 ns off).The signal is output through an IOBFF into the pin JC1 (V15), which drives a 180 ohm resistor. According to the reference manual, JC is one of the 3 high speed PMODS, but despite this my rise and fall times are around 5-7 ns.The slew rate is set to "FAST" and the  drive strength is set to "16".I want to decrease the rise and fall times to their absolute minimum value possible.

The code for generating the pulse :

    reg [1 : 0] counter = 0;
    always @ (posedge clk) begin
    if(!reset) begin counter <= 0; gnd <= 0; pulse <= 0; end
    else       begin 
               counter <= (counter == 3)? 0 :  counter + 1;  //10MHz/4 = 2.5MHz , Period = 400ns
               pulse   <= (counter == 3)? 1 : 0;             //Pulse Length = 0.1us = 100ns
               gnd     <= 0;
               end
                           end

The 'gnd' signal from the code is connected to the adjacent pin(JC2).

I am also attaching images of the observed waveforms (both rise and fall) .The oscilloscope uses a BNC cable which is terminated at 50 ohms.To reduce measurement inaccuracy, I have tried to keep the ground wire short. The 180 ohm resistor,directly connected to the PMOD header, is being used to limit the current drawn from the pin.The fall time seems to be less than the rise time by about 1 ns, but it still is 5 ns, at least. What can I do to reduce the rise and fall time of an IO?

From what I understand, using a higher frequency clock or an ODDR would have no effect as the switching should really be governed only by the DC characteristics. 

Thank you!

rise time.jpg

fall time.jpg

measurement.jpg

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Dear @techno-rogue

It is not clear what is your goal. Do you want to use Zybo as a signal source for some 50 Ohm load or it will interface some kind of digital logic? If the goal is the first one then your experiment can be representitive. However you need to account for the capacitance of the 50 Ohm cable and the bandwidth of the scope you are using. Typically measurements of ns pulse are done using special scope hih impedance probes with very small input capacitance.

If your load is some digital logic then the experiment is not representitive because most of 3.3V logic is CMOS and its input is pure capacitance with some loss component.

In my experience I was able to drive 40 MHz clock to my custom logic out of Zybo Pmod. I didn't try higher since it was no need. Higher rates can be achived using LVDS but Zybo is not equipped for this.

Hope you find it useful.

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Dear @Notarobot
My goal is to use the output signal of the PMOD, transmit it down an RF cable with a characteristic impedance (Zo) of 50 ohm.The cable will be connected to a 50 ohm load at the other end. I think the experimental setup discussed above differs only in the regard that there's a 180 ohm resistor at the pin.If I were to use a 50 ohm resistor at the source too, that might draw too much current.
Your reply points to potential issues with the scope and that may very well be the case.If its the scope, then could I generate a low frequency clock, with 50% duty cycle , and expect the rise and fall times then to be closer to the switching characteristics of the Zybo? Are you sure that nothing else could be the issue? Using an ODDR or a faster clock source shouldn't have any effect on the rise or fall time, should it?
Secondly, I have come across this post :

 The setup appears to be similar except that the probe used outputs 800 ohm resistance, but the Arty board is able to output a 100MHz clock with 1 ns rise and fall times.
 It would be extremely helpful if I could understand my inability to reproduce these results.
Thank you!

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@techno-rogue

I would suggest

1) check your scope measurements capability here

2) try to add a clock buffer at the Pmod output. Xilinx recommends to us such buffers for clocks. In VHDL it is

component BUFG
    port (  I : in STD_LOGIC;
                O : out STD_LOGIC);
end component;

 

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Dear @Notarobot

It seems you were right about the oscilloscope and the bandwidth criteria mentioned in the link you referred to in your last post.I was using a 100 MHz scope which  a is much less than the   (bandwidth = 0.3/rise time)  requirement for small rise times.I switched to a digital scope and was able to measure a rise/fall time of 1.6ns on the High-Speed PMOD, and a slightly slower, maybe around 2ns rise/fall time for JE, the standard PMOD.The high speed PMOD connection had a current limiting resistor in series, which was removed for the low speed PMOD (because of the default 200 ohm resistors on the standard PMOD of the Zybo).Is this the fastest the PMOD can go? I have the slew rate set to "FAST" and the drive at "16 " in the xdc constraints for the pin.

There's a lot of stuff available on scopes that helped me understand why what I was trying to do was wrong :
http://www.ni.com/white-paper/14825/en/

http://www.hobbyprojects.com/oscilloscope_tutorial/oscilloscope_probes.html

http://www.williamson-labs.com/scope-probes.htm

In addition to this, there's a helpful video on probe selection by the EEVBlog on youtube.

Thank you for your assistance, but is this the fastest the Zybo can go?

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Hi @techno-rogue

I might be wrong but it appears from the picture that the Pmod output is directly connected to 50 Ohms coax cable. The scope is showing about 2V amplitude which is inconsistent with the description of the experiment but consistent with the driving 50 Ohms directly from logic. Note that Zybo traces probably designed to have 60 Ohms impedance. Tail waves on the waveforms indicate impedance mismatch between 50 Ohms load and driving impedance.

If I would do such experiment I would interface Pmod using high speed line buffer and measure timing on its output. This is how design should be done and this way we would get realistic measurements.

Overall I think this is a good learning experience of electronic design theory in practice.

Good luck!

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Yes, you are absolutely right. I too was a little confused by the voltage level.I think I put the 50 ohm termination at the scope input in parallel with the 180 ohm resistor, but I realized that and fixed it today with the digital scope.The 1.5ns readings I obtained are definitely with the resistor in series.

Okay, so from what you're saying, here's the picture I build in my head.
A trace with a characteristic impedance of 60 ohms carries the signal from the source to the PMOD.In order to match this impedance, the pin needs to see 60 ohms at its end.Is this correct?
If so, the simplest topology that comes to mind is terminating the line with a 60 ohm resistor connected to the ground.However, doing so would draw too much current = (3.3/60)?.
From what I know the buffer would have infinite resistance and serves only to isolate the pin before the signal is put on the coax to its destination elsewhere.Is this right?
How accurate is the model being discussed in the following link(the diagram with the output buffer,output impedance Ro and the input buffer)?
https://forums.xilinx.com/t5/General-Technical-Discussion/Resistor-termination-for-FPGA-to-SPI/td-p/160122
The replies there seem to suggest that simply matching the coax cable's impedance with the sum of the pin's output resistance and a series resistor would is enough.It doesn't include any discussion of terminating the internal trace impedance, why?
All of this is based on the assumption that I've understood what you said correctly. Thank you for your time!

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Ok, I think I wrote the last post a bit too hastily.In Xilinx Document ug471, there's plenty of description of the DCI, which helps clear up a few things.Moreover, Fig 1-39 shows the conventional method of unidirectional termination for LVCMOS33.

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Definitely do not follow Notarobot's advice and put a BUFG on any clock output. BUFGs are only used to provide access to the special *internal* clock buses in the FPGA and provide no benefit on an output. In fact, the correct way to output a clock in a Xilinx FPGA uses the DDR2 component. For example:, in VHDL:

      clk_ddr2 : ODDR
        port map (D1 => '1', D2 => '0', C => internal_clk, CE => '1', R => '0', S => '0', Q  => clk_b);
      clk_obuf : OBUF
        port map (I => clk_b, O => CLK_OUT);

This is necessary because the internal low-skew clock buses have no direct connection to an I/O pin, just to the "C" (clock) input of the output flip flops. So you have to jump through some hoops to actually output the clock. This is something all Xilinx developers become familiar with very quickly.

Edited by jadwin79

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Hi,

have a look at the configuration of the output driver (DRIVE and SLEW constraints e.g. DRIVE=24 and SLEW=FAST).

That said, on a CMOD A7 board with a 4 GSPS scope I see slightly less than 4 ns rise time (10..90 %) from the unprotected IOs. The PMODs outputs with 200 ohms are worse, unsurprisingly.

The question of cable termination is a tricky one. Depends really on what you want to achieve. For example,
- you can drive with 0 ohms and terminate the remote end with 50 ohms. In this case, you can place high-Z inputs all along the cable
This works because the incident wave does not get reflected at the terminated cable end. Thus the driver does not need to terminate any reflection and its mismatch does not matter

- you can drive with 50 ohms and leave the remote end unterminated with a high-Z input. In this case, only the cable end shows the "correct" step response. An observer anywhere else on the cable sees a stairstep response from the incident wave (half voltage) and the reflected wave (half voltage). For the observer at the end of the cable, the two waves coincide and it seels a clean, full voltage step.

- if you drive 50 ohms and terminate 50 ohms, cable reflections are suppressed both ways but you lose half the voltage.

This only as something to think about, not as an exhaustive answer.

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Correction: With an active probe it's below 3 ns (10..90 %, CMOD A7 direct IO) with questionable ground wiring.

Still, most likely this is partly due to the probe with its nominal 3 dB bandwidth of 1 GHz.

 

 

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