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aytli

Zybo Z7-10 HDMI demo stuck at route_design

Question

I've been trying to get the Zybo Z7-10 HDMI demo (link) to run on my board, but I can't seem to be able to compile the actual project (using Vivado 2017.3 on Windows 10). I created the project from the create_project.tcl script in the proj folder, and was able to generate the block diagram and wrapper. I upgraded the IP cores and verified that the xdc file was consistent with the wrapper. But when I try to generate a bistream, Vivado always seems to get stuck on route_design. I've left Vivado running for 4 hours and it still can't move past route_design, despite it still using ~30% of my CPU. From these two forum posts, could it be a version problem? I don't seem to have a system.tcl file in my project.

I've been able to run the demo on my board by loading the provided bitstream and running the example code, but I would like to modify the demo and use it as a starting point for my project.

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Hi @aytli,

The projects are made and supported on a specific version of Vivado. In this case it is Vivado 2016.4.  Unfortunately, we do not support our projects on every version of Vivado. My understanding is that we will update/support most of our projects to 2017.4 and then to 2018.4....and so on.  I am glad you were able to generate a bitstream in much less time using Vivado 2016.4. For the HDMI project being used in sdk 2016.4 ,after programming the fpga in sdk right click on the application you imported then click run as->launch on hardware(system debugger). If this process does not run the application on the board please copy the sdk log and error messages to a text file and post it on this thread.

cheers,

Jon

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Hi @aytli,

Version is an issue with directly running these project. You can find the tcl script here: Zybo-Z7-10-HDMI/src/bd/system/hw_handoff/system_bd.tcl. You need to edit the "2016.4" to the version you are using "2017.3". Make sure that you have downloaded the vivado library from here and placed the contents in the folder here: Zybo-Z7-10-HDMI/repo/vivado-library. Then launch the project in vivado 2017.3. Once it is loaded upgrade/generate the ip cores tools->reports->report ip status. Next you will need to create a wrapper and then generate a bitstream. You then export hardware including bitstream and launch sdk. Once in sdk import the applications from the sdk folder, program the fpga and then right click on the application and run as->launch on hardware(system debugger). 

cheers,

Jon

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Hi Jon,

Thanks for the response, I checked the version number in system_bd.tcl and it was already set to 2017.3, I haven't had to change it. I was actually able to get the project to compile this morning, shortly after I posted my question and before you responded. It took about 3 hours to generate a bitstream, but it and the demo code both worked. Right now I'm compiling the same block diagram again, just to see if Vivado always takes this long, and it seems to be hanging again. Looking at the properties of the route_design step, it seems to get stuck at 75% for a very long time.

Is there anything I can do to get Vivado's compile time down to something more reasonable, maybe under 30 minutes? I've been able to compile the HDMI-in demo for the older Zybo and it didn't take nearly as long.

EDIT: Second compile took about an hour, which is much better.

Edited by aytli

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Hi @aytli,

I updated a fresh download of the Zybo-Z7-10 HDMI project to Vivado 2017.3 and generated a bitstream in around 1 hour and 15 minutes. I was able to generate a bitstream with a fresh Zybo-Z7-10 HDMI project in Vivado 2016.4 in about 23 minutes. How many jobs did you have vivado using? what are your computers specs in regards to ram and type of cpu, # of cores, and speed of each core? 

thank you,

Jon 

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Hi Jon,

Thanks for the help, my laptop has an i7-7500U with 12GB of RAM, 2 cores at 2.7GHz. I only had one project running on Vivado.

Is there a reason why the bitstream takes that much longer in the newer version of Vivado? The 1h generation time I got last night is usable, but obviously faster is better.

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Hi @aytli,

It usually takes a little longer to generating a bitstream when upgrading a project from an older version of vivado.  I am not sure why this project takes much longer. A lot of times when i have seen an extended generation time in vivado it is dealing with timing.  I am using an i7, 16 GB or Ram and a quad core so that will shorten the time as well.  

cheers,

Jon

 

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Hi @jpeyron,

EDIT: I just tried programming another board (also zybo z7-10), and it worked. Maybe there was a problem connecting to my original board that caused this issue.

I've installed Vivado 2016.4, and I was able to get a bitstream for the HDMI demo in under 30 minutes. I'm able to program the FPGA, but I'm having trouble programming the ARM core. When I try to run the debugger, I get one of the following errors, none of which I can consistently recreate:

  • Memory write error at 0xF8000118. Cannot flush JTAG server queue. FT_Read returned 0, expected 12
  • Memory read error at 0xF8000108. Cannot flush JTAG server queue. FT_Write failed: io error
  • Memory write error, cannot access DAP, invalid ACK value

I've looked at the memory map generated by the linker (lscript.ld), and those addresses don't seem to be in any of the memory regions. Here's a picture of the memory map:

Quote

Capture.PNG.66b1f599b48f7f5cd6290a12572fadb7.PNG

 

On an unrelated note, the Zybo Z7-10 audio DMA demo also doesn't work properly on Vivado 2017.3. It compiles relatively fast, and I'm able to load both the bitstream and C code, but it has issues running with the demo code. I was able to use Vivado 2016.4 to generate a usable bitstream.

Edited by aytli

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