Vivado is slow - speedups?

[ntm]

I'm working on small designs for a computer architecture course with Nexys4 DDR boards.  Vivado seems pretty slow, maybe 3-4 minutes to go from verilog files to bitstream file on a Windows 8, Intel i5, 2.2GHz, 8GB RAM.

1. Is this "compile" time normal?

2. Are there ways to skip the optimization steps to make a less-efficient (space/run-speed wise) design, eg, is there a "gcc -O0 file.c" equivalent?

3. Is there any (time/speed) advantage to running Vivado commands in the shell rather than via GUI?

[D@n]

@ntm,

Is this "normal"?  Not at all.  The number you cite above is actually pretty fast.

There are settings that you can adjust.  From my standpoint, the defaults are usually set for pretty fast by default.  Hence, you can slow things down if you want to play with the parameters.

Is there anything else you can do?  Yes.  Take your Verilog design and run it through Verilator with the -cc and -Wall options.  That will often find any mistakes in your design in less time than it takes for Vivado to even start looking for syntax errors.  Even better, if you choose to, you may find that you can find problems using a Verilator based simulation faster than it takes Vivado to complete.

Dan