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circuitsense

Zybo Embedded Linux Hands on "Tutorial"

Question

I've een going through the Zybo Embedded Hands on Tutorial and I ------

 

- Cannot find zynq_ZYBO_config file for compiling UBOOT. It's not there in the master and master-next branch....

- Cannot find ramdisk Image on ZYBO webpage...

- Cannot proceed further...

 

IMHO the "tutorial" is not organized properly at all...

Is anyone at Digilent maintaining / reviewing all these documents before putting them up on the internet ?

 

Can anyone provide these files if they have ?

 

Thank You....

 

 

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Kaitlyn, Any chance you can put a date on your "instructables" tutorial (and keep the date on the Digilent copy up to date)? Makes it easier to tell if it has changed.

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Kernel finally booted !!

 

Changed the bootargs in zynq-zybo.dts to:

 

bootargs = "console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk rootwait devtmps.mount=1"

 

Then use the dtc utility to build the devicetree.dtb, do the rest of the stuff in the tutorial and watch the kernel boot.

..then make a bonfire and dance around it... :P

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Hello Everybody,

 

Sorry if it is not appropriate to write on already answered topic, but it seems to me that it is the best place for my question (since somebody successfully booted kernel on ZYBO board, by following this tutorial).

Unfortunately, I was not successful in booting kernel.

My first question is where to find proper device tree file (dts) for zybo board (zynq-zybo.dts) and which one to use? I did not find it on git (linux-Digilent-Dev). I have used master-next branch when cloning this repository. 

I did all the steps and when kernel starts booting form SD card, at some point message "bootconsole [earlycon0] disabled" appears and booting stops. 

Did anybody had similar issues? 

I believe that problem is with dts file I have, but I cannot prove it. :)

Can somebody send me working dts file for zybo board?

 

I googled a lot regarding this issue, but I was not successful. 

 

Thanks in advance.

Best regards,

lestrigonac

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Hello lestrigonac,

 

The DTS file is here. Could have attached it, but it did not allow me....[Error You aren't permitted to upload this kind of file]

https://gist.github.com/circuitsenses/727f4a04a8babed6c6f6

 

I hope your SD card is formatted as per the instructions here:

http://www.wiki.xilinx.com/Prepare+Boot+Medium

 

Place everything in the first partition. Hope this helps

 

Regards

- C.S

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Hello circuitsense,

 

Thank you for trying to help! :) 
 
I have tried with your DTS file and same problem is still present. I guess we have ruled out bad DTS file. :)
 
My SD card was formatted as it explained in "Getting Started With Embedded Linux – ZedBoard". Nevertheless, I formatted the SD card again with instructions you have pointed me to and again, same problem is still present.

 

I will try to attach log file from serial terminal, so maybe somebody can tell from it, where the problem could be. 

I would very much appreciate any help I can get.

 

@edit: Maybe it is important to mention that I use Vivado2014.4 WebPack on a Ubuntu 64-bit.

Also, I have just found online already prepared files for booting Linux on a Zybo board and it booted successfully.

Now I am even more confused, since I did same procedure several times and I really do not now what I did wrong.  

 

Thanks in advance,

Best regards,

lestrigonac

log.txt

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Dear Circuitsense,

 

your bootargs line made me boot linux too. Thanks a lot! I saw that two main differences from the line found in instructables or different pdfs that can be found arround is that you reference /dev/ram0 instead of /dev/ram and devtmps instead of devtmpfs. I am not a linux guru to tell what these differences mean but I will make some experiments and come back with other possible correct bootargs lines. For the time being, I am also starting to dance!

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I too am attempting to complete the Embedded hands-on Linux tutorial for Zybo - without success.

On a 32 bit machine, I have installed:  CentOS 6.6 and Vivado 2014.2 (WebPACK) with the SDK.

I've downloaded the appropriate files from the Digilent Zybo site (BSD, and the tutorial PDF).

I get through modification of the Block Design and attempt a bitstream generation which fails with a message about reset pins that are asynchronous.  The message suggests adding ps7 system reset IP which I did and connected, but there is then a place and route failure -

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    50 |    15 | LVCMOS33(15)                                                           |                                          |        |  +3.30 |    YES |     |
| 35 |    50 |    33 | LVCMOS33(25)  TMDS_33(8)                                               |                                          |        |  +3.30 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   100 |    48 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | AC_MCLK              | LVCMOS33        | IOB_X0Y0             | T19                  |                      |
|        | AC_MUTE_N[0]         | LVCMOS33        | IOB_X0Y3             | P18                  |                      |
|        | BLUE_O[0]            | LVCMOS33        | IOB_X0Y21            | P20                  |                      |
|        | GREEN_O[1]           | LVCMOS33        | IOB_X0Y22            | N20                  |                      |
|        | HSYNC_O              | LVCMOS33        | IOB_X0Y23            | P19                  |                      |
|        | VSYNC_O              | LVCMOS33        | IOB_X0Y49            | R19                  |                      |
|        | btns_4bits_tri_i[0]  | LVCMOS33        | IOB_X0Y9             | R18                  |                      |
|        | btns_4bits_tri_i[1]  | LVCMOS33        | IOB_X0Y1             | P16                  |                      |
|        | btns_4bits_tri_i[2]  | LVCMOS33        | IOB_X0Y14            | V16                  |                      |
|        | btns_4bits_tri_i[3]  | LVCMOS33        | IOB_X0Y36            | Y16                  |                      |
|        | iic_0_scl_io         | LVCMOS33        | IOB_X0Y24            | N18                  |                      |
|        | iic_0_sda_io         | LVCMOS33        | IOB_X0Y4             | N17                  |                      |
|        | sws_4bits_tri_i[1]   | LVCMOS33        | IOB_X0Y2             | P15                  |                      |
|        | sws_4bits_tri_i[2]   | LVCMOS33        | IOB_X0Y41            | W13                  |                      |
|        | sws_4bits_tri_i[3]   | LVCMOS33        | IOB_X0Y32            | T16                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | HDMI_CLK_P           | TMDS_33         | IOB_X0Y74            | H16                  |                      |
|        | HDMI_CLK_N           | TMDS_33         | IOB_X0Y73            | H17                  |                      |
|        | HDMI_D0_P            | TMDS_33         | IOB_X0Y92            | D19                  |                      |
|        | HDMI_D0_N            | TMDS_33         | IOB_X0Y91            | D20                  |                      |
|        | HDMI_D1_P            | TMDS_33         | IOB_X0Y98            | C20                  |                      |
|        | HDMI_D1_N            | TMDS_33         | IOB_X0Y97            | B20                  |                      |
|        | HDMI_D2_P            | TMDS_33         | IOB_X0Y96            | B19                  |                      |
|        | HDMI_D2_N            | TMDS_33         | IOB_X0Y95            | A20                  |                      |
|        | AC_BCLK[0]           | LVCMOS33        | IOB_X0Y75            | K18                  |                      |
|        | AC_PBLRC[0]          | LVCMOS33        | IOB_X0Y77            | L17                  |                      |
|        | AC_RECLRC[0]         | LVCMOS33        | IOB_X0Y83            | M18                  |                      |
|        | AC_SDATA_I           | LVCMOS33        | IOB_X0Y76            | K17                  |                      |
|        | AC_SDATA_O[0]        | LVCMOS33        | IOB_X0Y84            | M17                  |                      |
|        | BLUE_O[1]            | LVCMOS33        | IOB_X0Y85            | M20                  |                      |
|        | BLUE_O[2]            | LVCMOS33        | IOB_X0Y80            | K19                  |                      |
|        | BLUE_O[3]            | LVCMOS33        | IOB_X0Y72            | J18                  |                      |
|        | BLUE_O[4]            | LVCMOS33        | IOB_X0Y64            | G19                  |                      |
|        | GREEN_O[0]           | LVCMOS33        | IOB_X0Y71            | H18                  |                      |
|        | GREEN_O[2]           | LVCMOS33        | IOB_X0Y82            | L19                  |                      |
|        | GREEN_O[3]           | LVCMOS33        | IOB_X0Y79            | J19                  |                      |
|        | GREEN_O[4]           | LVCMOS33        | IOB_X0Y65            | H20                  |                      |
|        | GREEN_O[5]           | LVCMOS33        | IOB_X0Y69            | F20                  |                      |
|        | HDMI_OEN[0]          | LVCMOS33        | IOB_X0Y87            | F17                  | *                    |
|        | RED_O[0]             | LVCMOS33        | IOB_X0Y86            | M19                  |                      |
|        | RED_O[1]             | LVCMOS33        | IOB_X0Y81            | L20                  |                      |
|        | RED_O[2]             | LVCMOS33        | IOB_X0Y66            | J20                  |                      |
|        | RED_O[3]             | LVCMOS33        | IOB_X0Y63            | G20                  |                      |
|        | RED_O[4]             | LVCMOS33        | IOB_X0Y70            | F19                  |                      |
|        | led[0]               | LVCMOS33        | IOB_X0Y54            | M14                  |                      |
|        | led[1]               | LVCMOS33        | IOB_X0Y53            | M15                  |                      |
|        | led[2]               | LVCMOS33        | IOB_X0Y99            | G14                  |                      |
|       | led[3]               | LVCMOS33        | IOB_X0Y93            | D18                  |                      |
|        | sws_4bits_tri_i[0]   | LVCMOS33        | IOB_X0Y61            | G15                  | *                    |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

My newbie eyes see there's maybe a problem routing to the switches on the board?  I would have thought the published BSD would not generate such errors since I did not modify that.  The same goes for the reset pins problem I described above - I wouldn't think the BSD would be incorrectly configured.

My question is whether using Vivado 2014.2 is causing this problem and the reset pins problem?  That is, would it be worth my time to install 2014.1 (specified in the tutorial PDF) and try again?

I am a newbie to Zynq and I want to learn this - the tutorial describes things I know I need to learn and I'd just like to get through a successful run.  I've read elsewhere on the fora here that the Zybo Basic System Design may need some work - and I can wait for that to be able to use higher versions of Vivado (when I get a 64 bit system), but as I said, I'd just like to get through a successful run, all the way to the end.

Any suggestions would be very much appreciated.

Edited by JovianPyx

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I decided to try compiling the unmodified Zybo Base System Design in both Vivado 2014.2 and 2014.1.  Using 2014.2, I get the placer error above.  Using 2014.1, Vivado completes successfully.  So something about the BSD itself is unappreciated by Vivado 2014.2. 

In both of the runs, there were numerous critical warnings about asynchronous resets which I simply ignored.

Hopefully the folks at Digilent will fix the BSD soon.

Next is to use 2014.1 to attempt the entire tutorial.  I will post about that later when I'm finished doing it.

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Vivado 2014.1 does indeed eliminate the placer error.  However, Vivado will not produce a system.bit file with a successful compile.  In some Xilinx forum post, I found that CentOS 6.6 is not supported, but CentOS 6.5 is.  I may still have an issue since the specified platform is 64 bit, however, I am going to download CentOS 6.5 32 bit and try again.  The failure (as I read from the thread) is due to a Java problem.  I did, in fact, see a Java error while installing Vivado 2014.1 on CentOS 6.6, but I decided to go forward and see what happens.

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Just for grins, I tried to compile the unmodified Zybo base system design using Vivado WebPACK 2014.1 for 32 bit Windows.  During implementation an error message window appeared saying "xilcurl.exe is not a valid win32 application".  Googling that yielded no hits.  No system.bit was created.

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Hi JovianPyx,

I've contacted our support team so they are aware of this and they'll get back to you here on the Forum.

Thanks,
JColvin

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Ah, thank you very much. 

I would like to add that while no system.bit was generated, a system_wrapper.bit was generated with a fresh time stamp in the proper project location.

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