Hayder

External 7 segment connnected with Zybo

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Hello

This is the second project for me in FPGA for fun.

I want to connect external board with 7 seg as a counter, so I put this Verilog code with this XDC file but the output is something error , could you please figure it out?

I use common Anode display

PMOD XADC

pin 1 ---> pin 12 (7 Seg)

pin 2 ----> Pin 9

pin 3 ---> Pin 8

pin 4 -----> pin 6

------------------------

PMOD JB

pin 1 ---> pin 11

pin 2----> pin 7

pin 3-----> pin 4

pin 4 ----> pin 2

pin 5 ----> pin 1

pin 6 ---> pin 10

pin 7 ----> pin 5

pin 8 ----> pin 3

 

Thanks

seven.v

Master_zybo.xdc

Edited by Hayder

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Hi @Hayder,

The errors help us determine what is wrong. Could you please copy and past the vivado errors into a text file and add to the thread. Also looking at the xdc you need to uncomment the second line of for the clock(line 17 in xdc). In your verilog code you declare 2 input buttons "input [1:0]btn" but in the xdc you only constrain btn[0]. So if you are using 2 buttons then you would need to uncommnent the second button on line 41 of the xdc. 

cheers,

Jon

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Hi @jpeyron

There are no errors in Vivado, the 7 segment display rubbish char...

After searching I found that my 7 segment is common cathode not common Anode, so please how can change the programming according to ?

just reverse lines 53,59,65

ja_p = 4'b0111;  ------> ja_p = 4'1000; ?

also reverse LED_BCD bits?

Thanks again

Edited by Hayder

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Hi @Hayder,

Here is a verilog code for a common cathode from fpga4fun that has three different example codes that should help you if there is an issue with the assignment of LED_BCD. The code you are using works off of the 100 Mhz clock of the basys 3. The zybo has a 125 Mhz clock when used as you are in the PL. The reference manual in section 12 details this. The change in frequency can also effect how the 7 segment display looks visually. You might want to use the clock wizard to change the clock to 100 Mhz. 

cheers,

Jon

Edited by jpeyron
Hayder likes this

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Hello @jpeyron

I wrote simple Verilog for displaying just one number

module one(
    output  [1:0] ja_p,
    output [6:0] jb_p
    );
    assign ja_p = 2'b0;
    assign jb_p = 7'b1111100;
   
endmodule

 

But I got strange char as in the attached picture !!

I connected my Display as:

A- 11

B- 7

C- 4

D- 2

E- 1

F- 10

G- 5

And when I remove one wire , the corresponding segment went off so I think the wiring is OK...

Thanks again for help

 

wrongeLED.jpg

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