New user - a little issue

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Hi All!

Just started looking at fpga's and hit a little wall :D

I bought a Arty Z7-20 and installed Vivado 2017.3

I found the guides to insert board files and inserted those into board_files, now some of the Digilent boards show up but not mine (i'm able to see Arty, Base3, Cmod's and several Nexys that have Digilent as vendor)

My system is a Windows 7, 64 bit machine.

Hope u can push me in the right direction!

Thanx in advance


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Hi @Skybird,

Make sure that you have downloaded our most current board_files here. Then copy the board files folder from this folder "vivado-boards\new" and paste it here: "C:\Xilinx\Vivado\2017.3\data\boards". I have attached a screen shot of what my folder look like with the path name visible. I have also attached a screen shot of what boards I have to select when setting up a project in vivado 2017.3. Could you have possibly added the board parts from the old folder here "vivado-boards\old\board_parts"? Can you attach screen shots of your folder with pathname and the boards available in Vivado 2017.3 like I did.





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Thank you for the assistance, i managed to get it working.

The thing i had to do was to use the Xilinx information center to do all upgrades of the software (there was one pending that i had not noticed).

Then i needed to enter the "Add design tools and devices" from Xilinx program folder in start menu.

In there i had to add the Zynx cpu's that i was missing + i also installed some other upgrades, after that my bord did show up in the menu and i could run a "Hello FPGA World" :D


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I got an Arty Z7-20 board and want to look at the UART.

I can't find a way to access the USB-UART bridge from verilog - fpga (i'm missing the RX and TX pin)

I found this in the board referance:


I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller.

What does this mean?

On the Arty board i found that A9 and D10 was the RX / TX.



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Hi @Skybird,

The Arty-Z7-20 has a ZYNQ processor on it. Many of the components are directly tied to the ZYNQ chip and can only be accessed through the PS. The UART is one of these components. You will not be able to use the UART with an hdl design. You will be able to use the uart using the ZYNQ processor. The hello world application demonstrates the uart communication. In vivado add the zynq processor to the design. Next connect the FCLK_CLK0 to the M_AXI_ACLK. Then create a wrapper and generate a bitstream. Next export hardware including the bitstream and launch sdk. Once in sdk create an application. Name it whatever you would like and hit next. Choose hello world as the template. next open a serial terninal like tera term or use the one on the sdk. Make sure the baud rate is set to 115200. Next program the fpga and then run the program. I have included screen shots of the process as well as the zynq processor. Here is a tutorial that covers this as well. Also if you are looking to send and recieve through uart i would suggest to look at xuartps for zynq which will have putc/getc equivalent functions.

















Edited by jpeyron
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Thanx, i got that one up and running.

I also wanna say for others do press "Block automation" to make interfaces for fixed_Io & DDR when u need to get the interfaces made.

Now i need to figure out how the sdk and verilog part talk together :)


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It is possible to configure the UART 1 peripheral in the Zynq block to connect to the FPGA through EMIO. In this case, some super simple C code should be able to set up a passthrough.


Verilog modules can be added to a block design by right clicking in the Diagram pane and selecting "Add Module". You can then manually connect the module's rx and tx pins to the TX and RX pins of the Zynq block's new UART_1 interface.


The C source would look something like the following (note I haven't tested this):

#include "xuartps.h"
#include "xparameters.h"
typedef XUartPs_Config *XUartPs_ConfigPtr;

int main()
    u32 device_ids[2] = {XPAR_PS7_UART_0_DEVICE_ID, XPAR_PS7_UART_1_DEVICE_ID};
    u32 base_addrs[2] = {XPAR_PS7_UART_0_BASEADDR, XPAR_PS7_UART_1_BASEADDR};
    XUartPs uarts[2];
    XUartPs_ConfigPtr uart_cfgs[2];
    int i;
    u32 bytes_received;
    u8 buffer[1];

    for (i=0; i<2; i++)
        uart_cfgs[i] = XUartPs_LookupCfg(device_ids[i]);
        XUartPs_CfgInitialize(&uarts[i], uart_cfgs[i], base_addrs[i]);
    while (1)
        bytes_received = XUartPs_Recv(&uarts[0], buffer, 1);
        if (bytes_received > 0)
            XUartPs_Send(&uarts[0], buffer, bytes_received);//echo back to PC
            XUartPs_Send(&uarts[1], buffer, bytes_received);//forward to FPGA
    return 0;

Have fun!


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