Pmod OLEDrgb: 96 x 64 RGB OLED Display Power Up

[fdstreetman]

Hi,

I am reviewing your page: https://reference.digilentinc.com/reference/pmod/pmodoledrgb/reference-manual steps 1 through 4 vs the schematic: https://reference.digilentinc.com/_media/reference/pmod/pmodoledrgb/pmodoledrgb_sch.pdf and datasheet, page 27: https://cdn-shop.adafruit.com/datasheets/SSD1331_1.2.pdf.

 

To me, seems like there is a conflict on the power on sequence.  On the reference manual page, this is the order

Quick Data Acquisition

Power-on Sequence where the bytes provided are in the format of (command, data)

1. Bring Data/Command control (pin 7) logic low.

2. Bring the Reset pin (pin 8) logic high.

3. Bring the Vcc Enable (pin 9) logic low.

4. Bring Pmod Enable (pin 10) to logic high and delay 20 ms to allow the 3.3V rail to become stable.

5. Bring RES (pin 8) logic low, wait for at least 3 us, and then bring it back to logic high to reset the display controller.

6. Wait for the reset operation to complete; this takes a maximum of 3 us to complete.

 

But on the datasheet page, P27, this is the order.

Power ON and OFF sequence
The following figures illustrate the recommended power ON and power OFF sequence of SSD1331 (assume VDD and VDDIO are at the same voltage level).

Power ON sequence:
1. Power ON VDD, VDDIO.
2. After VDD, VDDIO become stable, set RES# pin LOW (logic low) for at least 3us (t1) and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 3us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 100ms (tAF).

 Vcc Enable(VCCEN) turn on Vcc first and it happens BEFORE the RES(reset) goes low in your reference manual BUT the datasheet has Vdd, Vddio coming on first which is Pmod Enable(PMODEN) and Vcc powers on AFTER reset goes low.

 Please Advise.

[jpeyron]

Hi @fdstreetman,

 

I'm a little confused about what you are seeing. Our setup does follow the recommended setup of having the Vdd and Vddio coming on first, and then the Vcc coming on after reset goes low and then brought back on high. You can see this with the Vcc enable being brought low (disabled) in step 3 and then the reset being brought low and then back high in step 8, followed by Vcc brought high (enabled) again in step 29.

cheers,

Jon

 

[fdstreetman]

Hi and Thank You.

From the schematic, the SHDN pin looks active high not active low. 

Again,

Thank You.

[D@n]

@fdstreetman,

Are we looking at the same schematic?  I'm looking at the schematic you referenced above, and I'm not seeing anything labeled SHDN.

Dan

 

[JColvin]

Hi @fdstreetman,

The SHDN pin on the step up converter (IC1) (http://www.ti.com/lit/ds/symlink/lmr62014.pdf) is active low according to it's datasheet that I linked to. So bringing Vcc enable logic low will prevent the step up converter from operating.

Thank you,
JColvin