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vonPuffelen

How to receive synchronous digital data with SDK

Question

I try to receive data with an Analog Discovery Kit (AD) from a FPGA written with my own protocol. Three signals enter the AD: Clock, Trigger, and Data. At the rising edge of the trigger, I would like to sample 16 bits from the data synchronous to the clock (around 20 Mhz). How can this be done with an AD and SDK? With an FPGA writing this is a matter of minutes, but some how I cannot wrap my head around this. Below is the code I am using, but sadly it returns only 0x0000 or 0x000.

How to receive data in this way?

Cheer,
VonPuffelen

FDwfDigitalInConfigure(AnalogDiscoveryHandle, false, true);  // start sampling
STS sts;
unsigned int timer = 0;// wait for receiving
do{
  if(!FDwfDigitalInStatus(AnalogDiscoveryHandle, true, &sts)) // pull for trigger event
  {
    printf("AcquireErro(42)");
    return 42;
  }
  timer++;
}while((sts != stsDone) && (timer < 0x1FFF));
FDwfDigitalInStatusData(AnalogDiscoveryHandle, data, length*sizeof(unsigned short)); // fetch data from IO buffer.
FDwfDigitalInConfigure(AnalogDiscoveryHandle, false, false);  // stop sampling

 

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Hi @vonPuffelen

The sync mode is not yet document in the SDK but here you have the instructions and example.
DigitalIn_Sync.py

# for sync mode set divider to -1
dwf.FDwfDigitalInDividerSet(hdwf, c_int(-1))
# in sync mode the trigger is used for sampling condition
# trigger detector mask:          low &     hight & ( rising | falling )
dwf.FDwfDigitalInTriggerSet(hdwf, c_int(0), c_int(0), c_int(1), c_int(0)) # DIO0 rising edge

 

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