Stupid Q: What does a loop in a HDL really mean?

[Tickstart]

I haven't used loops very much so far for this reason, I don't understand what they are in a hardware description language.

In a regular processor they are self explanatory, the processor cycles through the loop and tests the condition, one clock cycle at a time. But in VHDL for example, there is only one clock cycle.. So loops in a VHDL-process are some über-high abstraction thing that generates hardware that does all this seemingly sequential stuff in 1 clock cycle?

[D@n]

@Tickstart,

Yes.  Loops in HDL just generate more logic, not sequential logic.  Remember: *everything* runs in parallel.

"Sequential" loops in HDL have only the appearance of being sequential--they actually just describe logic.  If you can't fit the logic within one clock cycle, then you will fail to meet your timing constraints.

Dan

[Piasa]

loops can be used to describe HW.  normally this isn't done to describe complex HW though.

An example of a loops that can be useful in VHDL are:

parity (xor-reduce), any (or-reduce), none (not or-reduce), all (and-reduce), bit-reverse, bit-count (maybe), gf2 inner product, etc...

More complex logic like long-division or shift-add multiplication can infer much more logic.

very complex logic like a sorting algorithm would result in long synthesis times and likely a large, slow design.

[D@n]

@Tickstart,

Gosh, you want examples?  Let's see ...

• I've used loops in FIR filters to describe the logic required at each tap.
• I've used them within CORDIC's to describe the logic that neeeds to take place in a multi-stage algorithm. 
• I've used them to apply the same I/O logic to multiple bits in a vector.
• I've used them in loops to bit-reverse vectors.
• I've used them within my differential pmod-challenge code to look for bit-sync across multiple synchronization possibilities.
• I've used them to check for the synchronization sequence within an HDMI stream, knowing it could come in at any time and in any offset.
• I've used loops within initial statements, to initialize any memory that wasn't initialized by my $readmemh command.

Dan

[Gra]

its just a way of reducing the amount of HDL you have to type

 

Here is an example, say you want to describe a shift register, you have an input and an output data pin, say

 

input_port :  std_logic;

output_port :  std_logic;

 

you are going to need some flipflops for your shift register, lets have 8, you need an input to each flipflop and an output from each flipflop, here are some sigs for that 

 

input_signal :  std_logic_vector(7 downto 0);

output_signal :  std_logic_vector(7 downto 0);

 

 

then you need to describe the flipflops,

 

Process (....)

begin

if (clk ‘event and clk = ‘1’) then

output_signal <= input_signal;

end if;

end process;

 

Now you have 8 individual flipflops with inputs...

 

input_signal(0)

input_signal(1)

input_signal(2)

input_signal(3)

input_signal(4)

input_signal(5)

input_signal(6)

input_signal(7)

 

and outputs....

 

output_signal(0)

output_signal(1)

output_signal(2)

output_signal(3)

output_signal(4)

output_signal(5)

output_signal(6)

output_signal(7)

 

So to get your shift register you will need to connect the output of the first flipfloip to the input of the second flipflop and so on....

Then connect your  i/o ports, so something like this

 

 

input_signal(0) <= input_port

input_signal(1) <=output_signal(0)

input_signal(2) <=output_signal(1)

input_signal(3) <=output_signal(2)

input_signal(4) <=output_signal(3)

input_signal(5) <=output_signal(4)

input_signal(6) <=output_signal(5)

input_signal(7) <=output_signal(6)

output_port <= output_signal(7)

 

 

All a  loop does is compress the notation, the above  would do something like this...

 

 

i = 1 to 7 

input_signal(0) <= input_port

input_signal(i) <=output_signal(i-1)

output_port <= output_signal(7)

 

Useful notation if the shift register was much bigger, or you wanted to change the size easily, also useful in big repetitive circuits like hand crafted filters.

Not helpful when you are working in teams and they are used for something as simple as the above, as you can see its easier to read the long-hand description than a loop..

 

Hope that helps... Gra

[Piasa]

A shift register actually has fairly simple representations in both VHDL/Verilog.

sr <= sr(sr'length-1 downto 0) & something;

st <= {sr[`SRLEN-1:0], something};

Depending on how optimized the simulation/synthesis tool is, there could be a difference in performance.

[Gra]

Piasa,

 

it was actually an example to show a loop, not to demonstrate the best way to describe a shift register.

 

Gra