Clock/PLL for Cmod - A7?[SOLVED]

[bmentink]

Hi All,

Does anyone have some verilog for the clock/pll module instantiation .... I am getting stumped by the fact that the module won't accept 12Mhz input crystal as it is outside the range 19Mhz-800Mhz.

If someone can post the relevant code that I should have at the top level, it would be most welcome.

(PS: I am not using the GUI)

 

Cheers,

Bernie

 

[D@n]

@bmentink,

Ok, you got me on that one .... I was about to coach you in how to generate *any* frequency rate you needed with just a PLL and a little work, but then I checked the Artix-7 data sheet and you are right: the minimum clock speed going into the PLL is 19MHz.  Ouch.  I don't have an example that works in this case.

However .... the minimum speed going into the MMCM is 10MHz.  Further, Xilinx declares that the only difference between the two, on series-7 devices, is that the MMCM has more features. See if the MMCM will work for you.

By the way, if you aren't using the wizards, you may want to get familiar with the libraries guide.  That'll list all the *special* primitives Xilinx offers.  It should also list the manuals where the details of the components are explained.

Dan

[bmentink]

Thanks, I was using the PLL module not the MMCM module. I have changed that to this:

 

Quote

  MMCME2_BASE #(
      .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
      .CLKFBOUT_MULT_F(80.0), // 12*40=480MHz // Multiply value for all CLKOUT, (2-64)
      .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
      .CLKIN1_PERIOD(83.33), // (12MHz), Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
      // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
      .CLKOUT0_DIVIDE_F(12.0), // 80MHz
      // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
      .CLKOUT0_DUTY_CYCLE(0.5),
      // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
      .CLKOUT0_PHASE(0.0),
      //.CLKOUT4_CASCADE("FALSE"),
      .DIVCLK_DIVIDE(1), // Master division value, (1-56)
      .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
      .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
  )
  MMCME2_BASE_inst (
      // Clock Outputs: 1-bit (each) output: User configurable clock outputs
      .CLKOUT0(clk80gen),
      // Feedback Clocks: 1-bit (each) output: Clock feedback ports
      .CLKFBOUT(mmcm2_clk_fb_i), // 1-bit output: Feedback clock
      // Status Port: 1-bit (each) output: PLL status ports
      .LOCKED(locked_1), // 1-bit output: LOCK
      // Clock Input: 1-bit (each) input: Clock input
      .CLKIN1(CLK), // 1-bit input: Input clock
      // Control Ports: 1-bit (each) input: PLL control ports
      .PWRDWN(1'b0), // 1-bit input: Power-down
      .RST(1'b0), // 1-bit input: Reset
      // Feedback Clocks: 1-bit (each) input: Clock feedback ports
      .CLKFBIN(mmcm2_clk_fb_o) // 1-bit input: Feedback clock
  );

However I get an error:

Quote

The computed value 60.002 MHz (CLKIN1_PERIOD, net CLK_IBUF) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y0 (cell MMCME2_BASE_inst) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DI
VCLK_DIVIDE)).

I fon't know how it gets 60.002 MHz .... My calcs are 12Mhz x 80 = 960Mhz (within the vco) / 12 = 80Mhz my target frequency.

I must be missing something.

[D@n]

@bmentink,

What does your XDC file say about your clock?

Dan

[bmentink]

 

@D@n

Here you go:

 

Quote

## Clock signal 12 MHz
set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { CLK }];

 

[bmentink]

Ahhh ... my bad,  I had the multiply at 80 which exceeds the allowable 64, changed that to 60 and a divide by 9 and I am all good ....

Cheers,

B

[D@n]

@bmentink,

Good catch!  I was about to punt and hope someone else could solve your problem!

Dan

[bmentink]

Thanks for the help