Artix-A7 non-GUI development

[bmentink]

Hi,

While I am waiting for my brand new board to arrive, I am setting up the tools to do primarily non-GUI development. I.E  From a Linux shell I just want to create a Makefile project that runs the tools to do the symthesis/routing etc and programming.

I have installed the Vivado tools and have them running on the command line, so I can do a simple "make bitfile" and it will do it .. however, I can't seem to find any information on this site to do the programming of the FPGA ram or Flash with command line tools, can anyone help with that.?

Also, since I am programming in Verilog, there does not seems to be a lot of examples (apart from the ADC one) that I can reference, they are in in VHDL. It would be useful to have some more Verilog examples and some more howto's on non-GUI development.

Last question Can anyone explain the format of the board restraints (*.xdc) file, I can understand the 1st line below, but the meaning of the 2nd one eludes me:
 

Quote

 

#set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { pio[01] }];

#IO_L8N_T1_AD14N_35 Sch=pio[01]

 

Many Thanks

[bmentink]

@malexander

Cool, many thanks for that, just what I needed .... now just have to wait for my board to arrive to try it out.

Now the only an-answered question is the one above regarding GPIO bank allocation, I hope you might shed some light on that one. In the code:
 

module top(
  input wire CLK,
  input  wire DUO_SW1,
  input  wire RXD,
  output wire TXD,
  output wire LED,
  input  wire RXD1,
  output wire TXD1,

  inout wire [48:1] pio

  );

"pio" port is failing due to the router not being able to route the banks ... what do I need to do to my top level to rectify that. My board constraints file is pretty much default from Digilent site for this board ..

[malexander]

Off the top of my head I'm not sure why it's failing. Hopefully one of the guys from the applications team or support team will chime in.

[jpeyron]

Hi @bmentink,

Can you attach the errors that you are getting in vivado as well as your xdc and top file if you are able? 

thank you,

Jon

[bmentink]

@jpeyron

Sure, I have attached the xdc file, top file has some propriety stuff so can't post that ..

Here is the relavant error out of the verilog.log file:

 

Quote

 

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (10) is greater than number of available sites (0).
The following are banks with available pins:
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  BiDi RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 10 sites.
    Term: pio[2]
    Term: pio[3]
    Term: pio[4]
    Term: pio[5]
    Term: pio[6]
    Term: pio[7]
    Term: pio[8]
    Term: pio[9]
    Term: pio[24]
    Term: pio[25]

ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (10) is greater than number of available sites (0).
The following are banks with available pins:
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  BiDi RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 10 sites.
    Term: pio[2]
    Term: pio[3]
    Term: pio[4]
    Term: pio[5]
    Term: pio[6]
    Term: pio[7]
    Term: pio[8]
    Term: pio[9]
    Term: pio[24]
    Term: pio[25]

ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 14 |    50 |     5 | LVCMOS33(5)                                                            |                                          |        |  +3.30 |    YES |     |
| 16 |    12 |     2 | LVCMOS33(2)                                                            |                                          |        |  +3.30 |    YES |     |
| 34 |    24 |    22 | LVCMOS33(22)                                                           |                                          |        |  +3.30 |    YES |     |
| 35 |    20 |    12 | LVCMOS33(12)                                                           |                                          |        |  +3.30 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   106 |    41 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 14     | CLK                  | LVCMOS33        | IOB_X0Y26            | L17                  |                      |
|        | RXD                  | LVCMOS33        | IOB_X0Y36            | J17                  |                      |
|        | RXD1                 | LVCMOS33        | IOB_X0Y39            | G17                  |                      |
|        | TXD                  | LVCMOS33        | IOB_X0Y35            | J18                  |                      |
|        | TXD1                 | LVCMOS33        | IOB_X0Y41            | G19                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 16     | DUO_SW1              | LVCMOS33        | IOB_X0Y111           | A18                  | *                    |
|        | LED                  | LVCMOS33        | IOB_X0Y125           | A17                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | pio[26]              | LVCMOS33        | IOB_X1Y46            | R3                   |                      |
|        | pio[27]              | LVCMOS33        | IOB_X1Y45            | T3                   |                      |
|        | pio[28]              | LVCMOS33        | IOB_X1Y48            | R2                   |                      |
|        | pio[29]              | LVCMOS33        | IOB_X1Y44            | T1                   |                      |
|        | pio[30]              | LVCMOS33        | IOB_X1Y47            | T2                   |                      |
|        | pio[31]              | LVCMOS33        | IOB_X1Y43            | U1                   |                      |
|        | pio[32]              | LVCMOS33        | IOB_X1Y39            | W2                   |                      |
|        | pio[33]              | LVCMOS33        | IOB_X1Y40            | V2                   |                      |
|        | pio[34]              | LVCMOS33        | IOB_X1Y37            | W3                   | *                    |
|        | pio[35]              | LVCMOS33        | IOB_X1Y38            | V3                   |                      |
|        | pio[36]              | LVCMOS33        | IOB_X1Y26            | W5                   |                      |
|        | pio[37]              | LVCMOS33        | IOB_X1Y27            | V4                   |                      |
|        | pio[38]              | LVCMOS33        | IOB_X1Y28            | U4                   |                      |
|        | pio[39]              | LVCMOS33        | IOB_X1Y17            | V5                   |                      |
|        | pio[40]              | LVCMOS33        | IOB_X1Y25            | W4                   |                      |
|        | pio[41]              | LVCMOS33        | IOB_X1Y18            | U5                   |                      |
|        | pio[42]              | LVCMOS33        | IOB_X1Y31            | U2                   |                      |
|        | pio[43]              | LVCMOS33        | IOB_X1Y23            | W6                   |                      |
|        | pio[44]              | LVCMOS33        | IOB_X1Y32            | U3                   |                      |
|        | pio[45]              | LVCMOS33        | IOB_X1Y12            | U7                   |                      |
|        | pio[46]              | LVCMOS33        | IOB_X1Y24            | W7                   |                      |
|        | pio[47]              | LVCMOS33        | IOB_X1Y22            | U8                   |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | pio[10]              | LVCMOS33        | IOB_X1Y86            | J3                   |                      |
|        | pio[11]              | LVCMOS33        | IOB_X1Y93            | J1                   |                      |
|        | pio[12]              | LVCMOS33        | IOB_X1Y90            | K2                   |                      |
|        | pio[13]              | LVCMOS33        | IOB_X1Y87            | L1                   | *                    |
|        | pio[14]              | LVCMOS33        | IOB_X1Y89            | L2                   |                      |
|        | pio[17]              | LVCMOS33        | IOB_X1Y81            | M1                   |                      |
|        | pio[18]              | LVCMOS33        | IOB_X1Y76            | N3                   |                      |
|        | pio[19]              | LVCMOS33        | IOB_X1Y75            | P3                   |                      |
|        | pio[20]              | LVCMOS33        | IOB_X1Y82            | M2                   |                      |
|        | pio[21]              | LVCMOS33        | IOB_X1Y79            | N1                   |                      |
|        | pio[22]              | LVCMOS33        | IOB_X1Y80            | N2                   |                      |
|        | pio[23]              | LVCMOS33        | IOB_X1Y61            | P1                   | *                    |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

 

Thanks

CmodA7_Master.xdc

[jpeyron]

Hi @bmentink,

Looking at the   inout wire [48:1] pio you shared of your top module above and the xadc there is a discrepancy with pio[15] and pio[16] not being included in the xdc. I would suggest to re-number pio[17] through pio[48] to pio[15] through pio[46] and in the top module have  inout wire [46:1] pio. Let us know if this resolves the xdc error you are getting.

thank you,

Jon