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bmentink

Artix-A7 non-GUI development

Question

Hi,

While I am waiting for my brand new board to arrive, I am setting up the tools to do primarily non-GUI development. I.E  From a Linux shell I just want to create a Makefile project that runs the tools to do the symthesis/routing etc and programming.

I have installed the Vivado tools and have them running on the command line, so I can do a simple "make bitfile" and it will do it .. however, I can't seem to find any information on this site to do the programming of the FPGA ram or Flash with command line tools, can anyone help with that.?

Also, since I am programming in Verilog, there does not seems to be a lot of examples (apart from the ADC one) that I can reference, they are in in VHDL. It would be useful to have some more Verilog examples and some more howto's on non-GUI development.

Last question :) Can anyone explain the format of the board restraints (*.xdc) file, I can understand the 1st line below, but the meaning of the 2nd one eludes me:
 

Quote

 

#set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { pio[01] }];

#IO_L8N_T1_AD14N_35 Sch=pio[01]

 

Many Thanks

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This might be of interest to you https://www.xilinx.com/video/hardware/using-the-non-project-batch-flow.html (regarding none-GUI builds)

XDC files are a mystery, but here goes.

- Both lines are comments - they begin with hashs

- The second line is the true 'human readable' comment - the "Sch=" is the net naming in the schematic. . The IO_L8N... is the pin name on the FPGA package, It is in IO bank 35, it is the negative connection for LVDS pair 8 ("L8N"), and looks to also be the Negative input for XADC pair 14 ("AD14N").  Given the context it is pin M3 on the package being used.

So if you removed the first '#' on the first line, this is what is going on.

It applies the following settings:

   PACKAGE_PIN attribute is set to M3

   IOSTANDARD attribute is set to LVCMOS33

to the list of external connection that match those found by "get_ports" looking for things that match "pio[01]".

 

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@bmentink,

Programming an FPGA without using a GUI?  Sacrilege!!! :D

You can find my own attempts at building an FPGA design for the Arty-A7, without using any of the Vivado design methods, here.  The project includes programs that can be used for setting flash and RAM--once the device has been initially loaded.  You can also switch between configurations already loaded within the flash by just commanding the device to switch.  This is part of the design, though, and requires that the design be loaded in order to work.  Further, you can control the project (once loaded) over a TCP/IP port that gets forwarded through UART.

Hope this is what you are looking for,

Dan

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@hamster .. thanks

Still confused, that pin specified above is designated pio[01] a gpio pin, so what does it have to do with the XADC module? I thought only pins 15/16 was used for that ..

@D@n Wow that is a lot of code ... having trouble wading through it .. can you point me to the sections that do the programming?

Also, guys having trouble getting Vivado to route my design (because of my lack of understanding on the GPIO banks)

I have my "top" defined as:
 

Quote

 

module top(
  input wire CLK,
  input  wire DUO_SW1,
  input  wire RXD,
  output wire TXD,
  output wire LED,


  input  wire RXD1,
  output wire TXD1,

  inout wire [48:1] pio

  );

 

The placer through's up errors on some of the pio pins, says it cannot place them because of bank allocation. How should I specify the gpio's at the top level? The constraints file shows them as pio[1] to pio[48] but I have no idea how they are "banked"

Thanks again ..

Edited by bmentink

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1 hour ago, bmentink said:

Still confused, that pin specified above is designated pio[01] a gpio pin, so what does it have to do with the XADC module? I thought only pins 15/16 was used for that ..

Most of the FPGA pins can be used for multiple things -  inputs, outputs, global clocks, configuration, XADC, DDR memory.... as long as the pin can do what you want it to do you can the you are OK to ignore the other features (as long as you don't need to use the other feature!)

This is one of the differences between Xilinx and Altera FPGAs - Altera FPGAs usually have input-only pins, and high speed/low speed banks, making pin planning much more important for Altera.

Edited by hamster

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@bmentink,

Let's see ... the C++ program that loads flash or SDRAM with an ELF file can be found here.  It calls a fairly generic flash driver here.

Within the RTL code, it's all based upon a UART controlled wishbone master.  I describe a basic overview of how this bridge works here.  The wishbone master then connects to the peripherals through first an arbiter, and then an interconnect connects the wishbone bus master wires to their respective peripherals.  If you look through the peripherals, you'll find a flash peripheral as well as a wishbone-to-AXI bridge which is then used to control the MIG generated SD-RAM.  If you are interested, you can find a picture of how this bus is organized as a part of this blog post.

Dan

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@D@n

Thanks, but actually I was after the "Digilent" utilities to program the bitfile to FPGA/Ram and Flash via the USB/Jtag for Linux ... I don't need to do it programatically if I understand what you are doing correctly ... ;)   I only see reference of programming via Vivado GUI .. nothing from the command shell.

Anyone have any idea's about the banking issue on GPIO's?

Edited by bmentink

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@bmentink

You mean ... programming via the djtgcfg program?  I use that for my CMod-S6 core.  Take a look at the master make file, where I squirrel away how to use this program.  I've never tried it on my Arty.

Be aware that generic external programs will not work for loading SDRAM memory.  The problem with SDRAM memory is that you need to constantly refresh it at a fixed schedule, or the charge within the capacitors that form the memory will drain to zero.  What that means is that the values within SDRAM memory will not survive an FPGA configuration event.  Hence, a generic external program would fail since it would need to have the FPGA in its final configuration to load the SDRAM.  Most processors get around this by loading any initial memory they need into Flash, and then copying it from flash to SDRAM when the processor loads.  This woks when you have a processor on board, although there's no reason why you couldn't do that without--you just need to put a lot of infrastructure in place first.

Dan

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@D@n

So where do I get djtgcfg?? Search of the Digilent site shows nothing .... surely they should have a reference to command-line programming utilities somewhere on the cmod-a7 page??Why all this focus on damm GUI's grrr ...

I don't need to load SDRAM ... just FPGA/SRAM and Flash.

I have a Soft CPU as well, but it only needs to use SRAM ... (It's a small 32-bit Forth CPU)

 

PS: I am porting a project that ran on a Spartan-6 and used ISE tools ..

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@bmentink,

If I recall correctly, djtgcfg is part of the Adept2 utilities.

A 32-bit forth CPU?  I've seen 8-bit forth CPU's.  A 32-bit forth CPU almost sounds ... relevant.  :D

Dan

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@D@n

Hmm, the only binary Adept2 seemed to install was "dftdrvdtch" and typing that in a console does nothing ... why is this so hard? The Adept2 manual states: "A command-line data transfer program is provided to demonstrate the Adept SDK API." but nothing on how to use it ....

 

Yes, there are many 32-bit Forth's around, they are in use everywhere .... even on space sattelites and missions to planets .... almost relevant,  like you said ;)

( I am actually 10x more productive and bug free programming in Forth than C/C++ .... but that's a whole nother story, but some of the reason Forth is used in mission critical stuff)

 

Edited by bmentink

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For linux there is just a tar-ball which I un-compressed and ran the install.sh script .... it sucessfully placed stuff all over my system.

On the Adept2 page there is no mention of utilities or SDK just runtime ..... like I say, why is this so hard?

The README in the tar-ball  talks all about installing, nothing about using the code ....

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Thanks, found it. Now I presume that will allow programming a bit file to the FPGA. What do I have to do to get a "Flash programming" bit file that will get loaded 1st and then load my bit file into flash?  ..... at least, that was the method I have used in the past to program flash on Spartan-6 with Papillio-duo/pro boards ...

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Hi @bmentink,

Once you download and install Adept 2 utilities, runtime and sdk you should be able to find the Digilent Adept 2 sdk folder which has examples and documentation. On my windows machine the folder was added hereHere is the Cmod-A7 resource center. On the Cmod-A7 resource page there is a tutorial on how to program the flash from sdk here and how to program flash from the hardware manager in Vivado here. Adept 2 does facilitate the ability to program flash for the older fpga's like the Spartan-6 and the Spartan-3E but unfortunately not for the newer fpga's like the  Artix 7.

thank you,

Jon

adept2_flash_1.jpg

adept2_flash_2.jpg

adept2_flash_3.jpg

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@jpeyron

Appreciate the reply, but you miss the point. As in the title, I want to do this WITHOUT the GUI !!!! THat means from the Linux command line .................

I am well aware of the links you posted .... please read the previous posts ....

Let me be as clear as I can: I want to use the djtgcfg utility to:

a) Configure the FPGA and run it .... this I beleive it can do.

bb) Configure the FPGA with a Digilent supplied bit file that will run and load the following bit file (my code) from USB to the flash 

That is how I am used to doing it with other chips .. where do I get THAT bit file??

 

Edited by bmentink

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Hi @bmentink,

I am sorry for the confusion. Here is a forum question that discusses the topic of programming flash from Linux command line. Unfortunately programming flash in Adept 2 is only available through the GUI. The Adept 2 GUI is not available in Linux. Adept 2 does not facilitate programming flash for the Artix7 from the GUI.  I would suggest to reach out to Xilinx support here to help you facilitate a programming flash from the command line in Linux.

thank you,

Jon  

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@jpeyron

Why should I go to Xilinx, they do not make the board, Digilent does, so they should provide command line programming tools for Linux ... surely.

How will Xilinx help unless they have boards with exactly the same layout of FTDI and Flash chip .... even more confused.. ...

 

Thanks

Edited by bmentink

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 Vivado has integrated support for the programming circuit on the CmodA7 so you can program both the FPGA and the flash using Hardware Manager. If you want to do this from the command line then the easiest way is with TCL scripts. I've attached the TCL scripts that we use to program the user demo into the flash during the manufacturing test. On a Windows machine you would use these by opening a command prompt, changing to the directory that contains both prof_flash_15t.tcl (or the other one in the case of the 35T) and CmodA7_User_Demo-15T.bin, and then executing "vivado -mode batch -source prog_flash_15t.tcl". The process should be very similar in Linux. If you want to program a bin file with a different name into the flash then you will need to modify the TCL script.

prog_flash_15t.tcl

prog_flash_35t.tcl

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@malexander

Many Thanks, so presumable I have to start a hw server somehow first?

Presume the line below has to be modified to load my .bit bitstream file?

set_property PROGRAM.FILES [list "./CmodA7_User_Demo-35T.bin" ]

Also, do you have a modified version that just loads the FPGA?

Edited by bmentink

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No you don't need to launch hardware server - the first line of the TCL script does that.

You can use djtgcfg from the Adept Utilities package to program the FPGA. If I remember correctly the syntax is something like "djtgcfg prog -d <device_username> -i 0 -f config.bit". You can use "djtgconfig enum" to figure out the username string. I think the default for that board is CmodA7 so executing "djtgcfg prog -d <device_username> -i 0 -f config.bit" may do the trick, provided that config.bit is the name of the bitfile you want to load and that your current working directory contains that file.

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@malexander

Cool, many thanks for that, just what I needed .... now just have to wait for my board to arrive to try it out.

Now the only an-answered question is the one above regarding GPIO bank allocation, I hope you might shed some light on that one. In the code:
 

module top(
  input wire CLK,
  input  wire DUO_SW1,
  input  wire RXD,
  output wire TXD,
  output wire LED,
  input  wire RXD1,
  output wire TXD1,

  inout wire [48:1] pio

  );

"pio" port is failing due to the router not being able to route the banks ... what do I need to do to my top level to rectify that. My board constraints file is pretty much default from Digilent site for this board ..

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Off the top of my head I'm not sure why it's failing. Hopefully one of the guys from the applications team or support team will chime in.

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Hi @bmentink,

Can you attach the errors that you are getting in vivado as well as your xdc and top file if you are able? 

thank you,

Jon

Edited by jpeyron

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@jpeyron

Sure, I have attached the xdc file, top file has some propriety stuff so can't post that ..

Here is the relavant error out of the verilog.log file:

 

Quote

 

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (10) is greater than number of available sites (0).
The following are banks with available pins:
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  BiDi RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 10 sites.
    Term: pio[2]
    Term: pio[3]
    Term: pio[4]
    Term: pio[5]
    Term: pio[6]
    Term: pio[7]
    Term: pio[8]
    Term: pio[9]
    Term: pio[24]
    Term: pio[25]


ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (10) is greater than number of available sites (0).
The following are banks with available pins:
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  BiDi RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 10 sites.
    Term: pio[2]
    Term: pio[3]
    Term: pio[4]
    Term: pio[5]
    Term: pio[6]
    Term: pio[7]
    Term: pio[8]
    Term: pio[9]
    Term: pio[24]
    Term: pio[25]


ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 14 |    50 |     5 | LVCMOS33(5)                                                            |                                          |        |  +3.30 |    YES |     |
| 16 |    12 |     2 | LVCMOS33(2)                                                            |                                          |        |  +3.30 |    YES |     |
| 34 |    24 |    22 | LVCMOS33(22)                                                           |                                          |        |  +3.30 |    YES |     |
| 35 |    20 |    12 | LVCMOS33(12)                                                           |                                          |        |  +3.30 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   106 |    41 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 14     | CLK                  | LVCMOS33        | IOB_X0Y26            | L17                  |                      |
|        | RXD                  | LVCMOS33        | IOB_X0Y36            | J17                  |                      |
|        | RXD1                 | LVCMOS33        | IOB_X0Y39            | G17                  |                      |
|        | TXD                  | LVCMOS33        | IOB_X0Y35            | J18                  |                      |
|        | TXD1                 | LVCMOS33        | IOB_X0Y41            | G19                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 16     | DUO_SW1              | LVCMOS33        | IOB_X0Y111           | A18                  | *                    |
|        | LED                  | LVCMOS33        | IOB_X0Y125           | A17                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | pio[26]              | LVCMOS33        | IOB_X1Y46            | R3                   |                      |
|        | pio[27]              | LVCMOS33        | IOB_X1Y45            | T3                   |                      |
|        | pio[28]              | LVCMOS33        | IOB_X1Y48            | R2                   |                      |
|        | pio[29]              | LVCMOS33        | IOB_X1Y44            | T1                   |                      |
|        | pio[30]              | LVCMOS33        | IOB_X1Y47            | T2                   |                      |
|        | pio[31]              | LVCMOS33        | IOB_X1Y43            | U1                   |                      |
|        | pio[32]              | LVCMOS33        | IOB_X1Y39            | W2                   |                      |
|        | pio[33]              | LVCMOS33        | IOB_X1Y40            | V2                   |                      |
|        | pio[34]              | LVCMOS33        | IOB_X1Y37            | W3                   | *                    |
|        | pio[35]              | LVCMOS33        | IOB_X1Y38            | V3                   |                      |
|        | pio[36]              | LVCMOS33        | IOB_X1Y26            | W5                   |                      |
|        | pio[37]              | LVCMOS33        | IOB_X1Y27            | V4                   |                      |
|        | pio[38]              | LVCMOS33        | IOB_X1Y28            | U4                   |                      |
|        | pio[39]              | LVCMOS33        | IOB_X1Y17            | V5                   |                      |
|        | pio[40]              | LVCMOS33        | IOB_X1Y25            | W4                   |                      |
|        | pio[41]              | LVCMOS33        | IOB_X1Y18            | U5                   |                      |
|        | pio[42]              | LVCMOS33        | IOB_X1Y31            | U2                   |                      |
|        | pio[43]              | LVCMOS33        | IOB_X1Y23            | W6                   |                      |
|        | pio[44]              | LVCMOS33        | IOB_X1Y32            | U3                   |                      |
|        | pio[45]              | LVCMOS33        | IOB_X1Y12            | U7                   |                      |
|        | pio[46]              | LVCMOS33        | IOB_X1Y24            | W7                   |                      |
|        | pio[47]              | LVCMOS33        | IOB_X1Y22            | U8                   |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | pio[10]              | LVCMOS33        | IOB_X1Y86            | J3                   |                      |
|        | pio[11]              | LVCMOS33        | IOB_X1Y93            | J1                   |                      |
|        | pio[12]              | LVCMOS33        | IOB_X1Y90            | K2                   |                      |
|        | pio[13]              | LVCMOS33        | IOB_X1Y87            | L1                   | *                    |
|        | pio[14]              | LVCMOS33        | IOB_X1Y89            | L2                   |                      |
|        | pio[17]              | LVCMOS33        | IOB_X1Y81            | M1                   |                      |
|        | pio[18]              | LVCMOS33        | IOB_X1Y76            | N3                   |                      |
|        | pio[19]              | LVCMOS33        | IOB_X1Y75            | P3                   |                      |
|        | pio[20]              | LVCMOS33        | IOB_X1Y82            | M2                   |                      |
|        | pio[21]              | LVCMOS33        | IOB_X1Y79            | N1                   |                      |
|        | pio[22]              | LVCMOS33        | IOB_X1Y80            | N2                   |                      |
|        | pio[23]              | LVCMOS33        | IOB_X1Y61            | P1                   | *                    |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+


 

Thanks

CmodA7_Master.xdc

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