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I'm newbie to FPGA, and start with ISE 14.7 , Zybo z7 and Make FPGA book by David Romano

the first example is make Frequency divider.

now I reach how to connect the virtual program to real I/O ports, but I find a lot of difficulties to put this into my board using PlanAhead 14.7

how to find these port in Zybo

- clock

- reset

- [31:0] bus output with just  2 bits bus tap.

- Voltage

thank you for your help


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Hi @Hayder,

I have not read the MAKE FPGA book by David Romano. I do not believe this is a book that we have on our store either. With that being said Here is a PlanAhead Tutorial that should be helpful. Just so you are aware ISE is no longer being supported by Xilinx. You will find more support with Vivado. Most of our examples and tutorials use Xilinx Vivado with our tutorial hereHere is the resource page for the Zybo Z7.  If you are looking to learn Verilog/VHDL i would also suggest to look at here.



Edited by jpeyron
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Hi @Hayder,

Unfortunately, All of our material for the Zybo uses Vivado. I have not used the planahead feature of ISE. Could you please attach a screen shot of the text and of what you are doing in planahead. Here is the Zybo's master XDC which is vivado's version of the UCF in ISE. I found an non Digilent UCF file on GitHub that was made for the Zybo here. I would also suggest to look through the digital section of our learn website here. It contains information on how to create a BUS as well as assign a reset and clock pin using the UCF.

thank you,


Edited by jpeyron
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Hello @jpeyron

in the book, the author uses Opal Kelly XEM6002. for the project which is

module BLinkLED_Sys2(

    input CLOCK_IN,

    input RESET,

    output OUT_HIGH,

    output OUT_LOW 



//-----Internal Variables-----


//---- internal signals

wire clk_in;

wire reset_in;

//------Code Starts Here------

assign clk_in = CLOCK_IN;

assign reset_in = RESET;

assign OUT_HIGH = blinkcount[21];

assign OUT_LOW = blinkcount[20];

always @(posedge clk_in) 

if (reset_in) begin 

	blinkcount <= 32'b0;




	blinkcount <= blinkcount + 1;



NOw to connect it with real FPGA pins he assumes 

CLOCK_IN ---> T8
RESET-----> M1
LGT1 (OUT_HIGH) ----> L1
LGT2 (OUT_LOW) -----> K1
Ground  -----> N/A
Power ------> N/A

my question is why he chooses pin 20. pin 21 is L! and K1?

also what is the same pins in Zybo which I use?


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Hi @Hayder,

Out_HIGH and OUT_LOW are assigned to bit 21 and 20 of the 32 bit register blinkcount. The always statement is a 32 bit counter using the register blinkcount.  T8,M1,L1,K1 are pins on the board the author is using. Their ucf file is constraining the inputs and outputs of the module BLinkLED_Sys2( CLOCK_IN, RESET, OUT_HIGH, OUT_LOW).  So you will need to decide what pins you want to assign to  CLOCK_IN, RESET, OUT_HIGH, OUT_LOW on the zybo. I provided a link to a UCF for the Zybo earlier for that purpose. I used that ucf file and altered it to work with your provided Verilog code. I used a button for the RESET, 2 different leds for OUT_HIGH and OUT-LOW and the clk for CLOCK_IN. I would suggest to look through the learn website I linked above as well. I explains how to use a UCF file. 




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