Clocking changing as a function of programming method on cmod-s6

[apailes]

Hello,

I am working with a cmod-s6 and have an application working properly when I program it using a bit file and the Digilent Adept program.  The application uses the 4 LED's on the board to indicate state and they change every second.  It also spits out RS232 data every second at 115.2 Kbaud.  All nice and happy when programed via Digilent Adept.  However,  When I program it by creating an MCS file, from the same bit file, and write this to the onboard SPI flash device using IMPACT as described is a post I found on this forum it runs about 4 times slower.  The application uses two DCM-SP, one to generate 50MHz from an 8MHz MEMs oscillator I've driven a pin with and the other to make 12.5 MHz from the same oscillator.  I'm using ISE 14.6 and have checked the CCLK configuration as recommended. 

Here is a copy of what I'm referencing when creating the MCS file.  I'll also attach the Verilog module that the DCM-SP reside in.

To me its the same bit file and should do the same thing no mater how its programmed.  What am I missing?

Thank you  for your help.

-Aaron

This can be programmed using Xilinx iMpact. 
1. Create BIT file using ISE
   - make sure the Generate Programming File/ Properties/ Startup Options/ FPGA Start-Up Clock is CCLK
   - otherwise iMpact will prompt and fix this CCLK option
   - optional: to speed up the boot process increase the "Configuration Rate" and "Set SPI Configuration Bus Width" to 4
2. Create .MCS file
   - start iMpact, (press No then Cancel)
   - Create PROM File, SPI Flash, Configure Single FPGA, ->, 128M(bit), Add Storage Device, ->, browse desired "Output File Location", OK
   - Add Device - OK, locate the earlier ISE generated BIT file, No, OK, Generate File...
3. Flash programming
   - start iMpact, (press No then Cancel)
   - Boundary Scan, Initialize Chain
   - Right click on SPI/BPI above the FPGA symbol, Add SPI/BPI Flash, locate the .mcs file, SPI PROM, S25FL128S, (optional: for faster programming set Data Width 4)
   - Right click FLASH, Program, OK

 

 

clk_gen_50MHz.v

[jpeyron]

Hi @apailes,

Unfortunately, I have not worked with impact in this was. I do know that Here is the Cmod S6 resource page. If you download the Cmod S6 factory-loaded demonstration project it has the source code along with both a bit file and mcs file available. I would suggest to load both bit and mcs file to verify that they are both functioning the same. Have you seen this tutorial here?  if you have not yet, It is the MCS File Creation with Xilinx ® ISE Tutorial. It uses ISE 11.1. I am unaware if there was a change in the process from ISE 11.1 and  ISE 14.6.  Are you following a guide or tutorial for the generation of the MCS file? If so please attach the link. 

cheers,

Jon  

[apailes]

Hello Jon,

I have been using the note numbered 2 in my original post to generate the MCS file from the bit file.  After reading your post I reviewed several other write ups on how to generate a MCS file including https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pim_p_configure_spi_bpi_through_fpga.htm.  I believe I'm doing the same thing.  I also used the MCS and bit from the demo project as you suggested and got both the bit and MCS to behave the same way.  I have tried regenerating the MCS file from my bit file, remaking the bit file using ISE and have not got the application running at the proper seed yet.  I measures the toggle rate and it is about 3.8 seconds instead of the expected 1 second.  I'm driving the cmod-s6 with a 8MHz MEMs oscillator who's accuracy is much better then 5% (1-3.8/4.0).  It almost as though the FPGA continues to run off CCLK.  The other thing I'm noticing is that programming takes about 300 seconds even if I try increasing CCLK to 16 or 22 from the default of 2. 

Thank you for you help

-Aaron

[jpeyron]

Hi @apailes,

I have reached out to more experienced co-workers to see if they have any more input for this thread.

cheers,

Jon

[apailes]

Thank you for reaching out.  I got it to partially work today by 1) adding a STARTUP_SPARTAN6 instance and using its EOS output as an input to a reset pipe and 2) Using the onboard 8MHZ clock that comes from the cmod-s6.  I'm trying to run the cmod-s6 from a MEM 8 MHz oscillator that sits on the board the cmod-s6 plugs into. I can occasionally get code to start with the MEMs.  I suspect some sort of start up issue between the FPGA and oscillator.  I think that this one is in my court.

Thank you for you help

-Aaron

[sbobrowicz]

@apailes

Sounds like an interesting problem... your guess is probably on the right track. Very strange behavior though. Check out the DCM_SP section here, it recommends also looping back a DCM STATUS bit and the LOCKED signal to the DCM reset in order to properly handle when an input clock goes out of spec:

https://www.xilinx.com/support/documentation/user_guides/ug382.pdf

Also check the Spartan 6 datasheet to make sure the oscillator is in spec:

https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

I'll also mention that I think your clocking scheme is a bit of a violation.Usually you want to drive the DCMs directly from a GCLK input, not from the global clock network. Also, you are only supposed to drive a single DCM with a single GCLK input. I may be wrong here and getting my 7-series architecture mixed up with the 6-series, so check me on this. If I'm right, you could try connecting your oscillator to two different GCLK inputs, assuming it has the drive strength to handle the additional capacitance. That would be cleaner.

One more tip: Try enabling bitstream compression to decrease Flash programming time.