HDMI DEMO Project - Problems VIVADO 2017.1

[Andrea_cau]

Hi, I have a lot of problem importing project.  I had imported HDMI project and I use zybo board.
https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start
When I started create_project.tcl vivado get me critical errors, so I decided to enter commands manually. 
I had errors because on create_project.tcl there aren't commands to upgrade the IP blocks.

I have resolved it.

now i have 193 warning and 1 critical warning (table1.xlsx file):

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Can you help me to correct this?

I can generate bitstream but i have a problem. After I had exported hardware and i had launch sdk I need to import project.

I have so many errors!!!!!

I attach sdk log txt file.

There is a big problem on include folder on the left menu.

I had try to add on HDMI_IN_bsp the ps7_cortexa9_0 folder that I have found in a forum , I have deleted hdmi-in.sdk folder from my project, and I try again export hardware, launch sdk, import project. I have resolve the problem of include folder on left menu but still I have problems with libraries. 

I think there are some compatibility problems in the project on Vivado 2017.1.

Do you know how i can fix it? Can you update the project?

Thanks

Andrea

Table1.xlsx

sdk log.txt

[Andrea_cau]

after import project on sdk 

Spoiler

 

 

[jpeyron]

Hi @Andrea_cau,

I an glad to hear your project is working. I would suggest to start a new thread.

thank you,

Jon

[Andrea_cau]

Hi guys,

I don't know why but yesterday my project decided to work.

Anyway I have downloaded yours updated projects.

Now, I have some questions. I need to create other thread or can I write here?

Thanks you for all 

Andrea

[toshas]

20 hours ago, Andrea_cau said:

Thanks you for all!
There are some errors but I can run the project!
thanks for all the time you have dedicated me.
I have other problem with SDK. I don't undestand why I can't edit some parts of the project. I tried to edit the menu: I deleted some xil_printf and I added some xil_printf and function and save it, then I programmed FPGA and I ran it. I didn't saw any change! The original menu appears on Console Tab. I don't understand where the programs found the original menu because I had save it after changed it.

Hi ululuk,
I tried to run 2017.3 project on vivado 2017.1.
Before I had modified version of vivado in hdmi_in17_3\src\bd\system.tcl file.
everything seemed to work very well, but when I tried to generate bitstream vivado failed to generate implementation.
attachments:
error table of 2017.3 project.

thanks for all the time you dedicate for me.

Andrea

2017_3.xlsx

Recheck XDC file it is a CASE sensitive. So top level port name should exactly match with names in XDC file.

ddc_* vs DDC_*

iic_* vs IIC_*

Best regards.

[jpeyron]

Hi @Andrea_cau,

Here is a link to my updated Zybo HDMI-IN Vivado 2017.1 compressed project. Please let us know if you are able to get this project working.

cheers,

Jon

[Andrea_cau]

if I add ps7_cortexa9_0 folder in C:\hdmi-in2\proj\hdmi-in.sdk\HDMI_IN_bsp I solve the includes problem but occur an errors (no target with id 64 in the system) and I can't run program with UART connection.

I'm altering the code in the file video_demo.c in sdk how I've ever did. ctrl+s and run (after the first run, select run or select run as->launch on hardware(system debugger) I think is the same but I had try both)

[jpeyron]

Hi @Andrea_cau,

I am glad you are able to get the project to work. Are you altering the code in the file vivdeo_demo.c in sdk, saving the changes and then right clicking on the hdmi-in application and selecting run as->launch on hardware(system debugger)? Or are you altering the code here: Zybo-hdmi-in-master\sdk\HDMI_IN\src\video_demo.c, saving and then right clicking on the hdmi-in application and selecting run as->launch on hardware(system debugger) ?

thank you,

Jon

[Andrea_cau]

Thanks you for all!
There are some errors but I can run the project!
thanks for all the time you have dedicated me.
I have other problem with SDK. I don't undestand why I can't edit some parts of the project. I tried to edit the menu: I deleted some xil_printf and I added some xil_printf and function and save it, then I programmed FPGA and I ran it. I didn't saw any change! The original menu appears on Console Tab. I don't understand where the programs found the original menu because I had save it after changed it.

Hi ululuk,
I tried to run 2017.3 project on vivado 2017.1.
Before I had modified version of vivado in hdmi_in17_3\src\bd\system.tcl file.
everything seemed to work very well, but when I tried to generate bitstream vivado failed to generate implementation.
attachments:
error table of 2017.3 project.

thanks for all the time you dedicate for me.

Andrea

2017_3.xlsx

[toshas]

Hi!

This project updated to 2017.3 is attached.

Dvi2rgb ip core was updated from 1.6 to 1.8.

And some minor modification was made in TCL scripts: vdma 6.2 -> 6.3, Vivado 2016.2 -> 2017.3, 720p_edid.txt -> dgl_720p_cea.data

Hope this will help to you!

 

Best regards.

 

hdmi_in_2017.3.rar

[jpeyron]

Hi @Andrea_cau,

In the first video it looks like you skipped generating the ips after you updated them. I would suggest generate the IP's after you have updated them.  Also in the second video you do not have to select the board it will auto detect when you are programming the fpga(I do not believe this will cause an issue thou). Next I right click on the HDMI-IN application and click on run as->launch on hardware(system debugger). Try this process instead of how you are launching the software on the fpga.  This should be all you need to do. Are you connecting to the Zybo through the USB J11 PROG UART? If yes, then you should be selecting to a com port. In my case it is COM42. I have attached screen shots of my process as well as the serial terminal being used in sdk. You can also use tera term if you would prefer. In my screen shots I do not have the HDMI or VGA connected. 

thank you, 

Jon

Spoiler

 

 

[Andrea_cau]

HI @ jpeyron,
thank you for everything you are doing for me and thank you all the time you are devoting me.
unfortunately I can not launch the program.
I made some videos. in the first and in the second video I followed your advice. in the third video I recorded what happens with my program. my program has a new bsp (i do not know how it works, a person has corrected the project because  ps7_cortexa9 include was not included.
1st:

2st:

3st: 

I'm at the beginning with the fpga so I do not know what I'm doing. to start the project they taught me to select run configuration -> 15200 -> jtag uart -> run. the first time I ran the program I had problems and they solved it for me. I used the program every day. Suddenly it stopped working. I have no way to solve it. I'm so sorry to take up your time with futile questions.
I hope you can notice from the videos what I'm doing wrong. thanks again soon!
Andrea

[jpeyron]

Hi @Andrea_cau,

When I use a new version of the vivado/sdk than what the project was made in there can be errors with not finding the expected versions of libraries in the sdk log. I just used Vivado 2017.1 and the Zybo-HDMI-IN made for Vivado 2016.4 with out having errors in the problems section of SDK. I re-loaded the project and the Vivado library from the zip file. Adding the contents of the vivado library folder to repo->vivado library. Next I edited the tcl script. Now I loaded the project by entering cd <pathname to proj folder in project> in the tcl console. with selecting the proj. Next i enter "source ./" and select  create_project.tcl. After the project loads i select report IP status and upgrade/generate the IPs. next I create a wrapper and then generate a bitstream. I then export hardware including the bitstream and then launch SDK. Once in sdk I import the HDMI_IN and HDMI_IN_bsp. After a minute or two the project should be fully loaded. I then program the fpga and run-lunch on hardwar(system debugger) without an error in the problem section of the SDK. At this point you can connect the HDMI and VGA and it should work along with launching a serial terminal or using the sdk teminal. I have included screen shots as well as my SDK Log. Another option is to install Vivado 2016.4 and this project will run without issues. We unfortunately do not have the staffing to update all of our project to every version of Vivado. We have been trying to update to every years .4 version I.E. 2015.4, 2016.4 and our next update should be 2017.4. 

cheers,

Jon

Spoiler

 

 

HDMI_IN_2017_1.txt

[Andrea_cau]

I searched for a solution, for example for (XSDB Server)ERROR: [Hsi 55-1594] Core axivdma of version 6.0 not found in repositories

https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf

in this file I found this: For cores targeting 7 series or Zynq®-7000 devices, UNIFAST libraries are not supported. Xilinx IP is tested and qualified with UNISIM libraries only. (screen shot)

I use zybo board. how can i solve it?

[Andrea_cau]

Thanks for all @jpeyron.

I did everything you wrote: I downloaded the library and copied it in the repo folder. I Edited hdmi_in_bd.tcl, etc. 

30.jpg and 31.jpg show the errors before generate bitstream, while from 32.jpg to 39.jpg after this

Spoiler

 

 

[jpeyron]

Hi @Andrea_cau,

I believe this is an issue with vivado from looking at the errors you are getting. Lets start with a fresh project that you have not loaded into vivado. Make sure that you have installed the contents of the vivado library from here in the vivado library folder in the repo folder.  Next you need the edit the hdmi_in_bd.tcl file using a text editor like notepad ++. You can find the  hdmi_in_bd.tcl file "Zybo-hdmi-in/src/bd/hdmi_in/hw_handoff/hdmi_in_bd.tcl". You need tot edit the "2016.4" to "2017.1". Then open the project in Vivado 2017.1 and upgrade the ips by clicking on tools->reports->report ip status and upgrade and generate the ips. Next create a wrapper by right clicking on the block design in the sources tab. Next you should be able the continue the process as normal.

cheers,

Jon

[Andrea_cau]

sdk: I can program FPGA but I Don't run the project:

edit by JColvin: I put the images in the spoiler tag

Spoiler

 

 

[Andrea_cau]

ok, on vivado:

edit by JColvin: put images in spoiler

Spoiler

 

 

[jpeyron]

Hi @Andrea_cau,

The file i suggest for you to edit is for generating a bitstream. And making sure the project is done correctly in vivado. To edit the file use a text editor like notepad ++. If you are at the point of running the program from SDK without any errors then you should not need to edit the file. Please attach a screen shot of the error along with you SDK. Are you able to see the zybo un the device manage under ports and universal serial bus controllers? I have attached a screen shot of my device manager with a zybo connected. What OS are you using? 

cheers,

Jon

[Andrea_cau]

Hi, 
I know where the file is, but I do not know how to edit it.
A person solved my BSP problem but he can't do anymore because is not my friend.
now I have other problem because I can't run "run configuration"
there are some errors:
-No Target with ID 64 in the System
-fpga configuration is not done on the target

I'm newbie and I don't know how to fix it
you could help me step by step, please?
Thanks
Andrea

[jpeyron]

Hi @Andrea_cau,

The HDMI-IN project takes HDMI input and outputs either the HDMI input or one of two test patterns through the VGA that can be altered based on selections from the serial terminal menu. The HDMI-OUT project outputs I believe two different test patterns that can be altered based on selections from the serial terminal menu. These two project gives you an example of how to use the HDMI in and HDMI out process. My directions should work for either project. The path names with change a little based on the project. I have attached screen shots of where you can find the tcl script on our github. The tcl scrip can be found in the same path in the project that you downloaded from GitHub. 

cheers,

Jon

[Andrea_cau]

What are the differences between HDMI_IN and HDMI_OUT?

what does " edit the hdmi_out_bd.tcl from 2016.4 to 2017.1 here:  Zybo-hdmi-out-master\src\bd\hdmi_out\hw_handoff." means? 

I'm a newbie

thanks for all. i use this version of HDMI_IN project https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start

[jpeyron]

Hi @Andrea_cau,

Unfortunately, The projects are version specific. We have upgraded the zybo hdmi projects from Vivado 2015.4 when they were made to Vivado 2016.4.  Here is a forum thread that describes the process of using the Vivado 2016.4 projects in Vivado 2017.1.  I would make sure that you are using the 2016.4 version of the project to use with Vivado 2017.1.  To clarify, you are able to generate a bitstream in vivado 2017.1.  In SDK I would suggest to delete the HDMI_IN_bsp then go to file->new board support package. Name the new BSP "HDMI_IN_bsp" and create it without adding any additional libraries. Let us know if this resolves the errors in SDK. 

thank you,

Jon

[Alex]

Is there any warning or error message in Vivado? 

[Andrea_cau]

yes, I have validated design.

[Alex]

Looks like you are missing some ips. Have you successfully repo all ips? You can validate the hardware design in Vivado and see which main IP is missing