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DVI to RGB IP Core - problems with resolutions above 720p


Hi Everyone,

I was trying to capturing hdmi signal and display video on VGA monitor using DVI to RGB IP Core (version 1.6 or 1.7). Everything works correctly for 800x600 1024x768 and 1280x720. But for other resolutions (1280x1024 1600x900 1680x1050 and 1920x1080) image on external VGA monitor has very poor quality. Could anyone suggest where is the problem. In dvi2rgb spec I've found info about constraining tmds clock so based on my calculation for ZYBO IP Core should work correctly for 1680x1050 resoultion (tmds clock is about 120). I am using this IP Core in bigger project and I need to explain where is the problem. I can also upload my project in Vivado.


Thanks for any help

Edited by kondzio9224
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Could you provide your project or at least a screenshot of your block design? I suspect that the problem lies in how PixelClock is being generated, but can't really tell exactly how the problem is being caused without seeing the design. Are you using the AXI_DynClk IP core from vivado-library? If you haven't already, referring to the Zybo HDMI IN demo may help.

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Here is the link to my google drive https://drive.google.com/open?id=0BwV4sdde6ENiU2l6TmM1RlVXNUk - there is project in vivado and an IP Core which includes dvi2rgb inside. But even if I try to use only dvi2rgb ipcore wideo for 1280x1024 and bigger resolutions are bad. 

"Are you using the AXI_DynClk IP core from vivado-library? If you haven't already, referring to the Zybo HDMI IN demo may help." - I don't use AXI_DynClk IP core.

Thank You:)


Screenshot from 2017-10-04 22-13-32.png

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This module I am trying to run on ZYBO and only 800x600 1024x768 and 1280x720 resolutions look good.

module hdmi_receiver_phy
      parameter reg kEmulateDDC = 1'b1,     // will emulate a DDC EEPROM with basic EDID, if set to yes 
      parameter reg kAddBUFG = 1'b1,         // true, if PixelClk should be re-buffered with BUFG 
      parameter     kClkRange = 2,   //  -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
      parameter     kEdidFileName = "720p_edid.txt",  // Select EDID file to use
      // 7-series specific
      parameter     kIDLY_TapValuePs = 78, //delay in ps per tap
      parameter     kIDLY_TapWidth = 5     //number of bits for IDELAYE2 tap counter   
    input wire              hdmi_clk_p,
    input wire           hdmi_clk_n,
    input wire [2:0]     hdmi_d_p,
    input wire [2:0]     hdmi_d_n,

    output wire          hdmi_hpd,
    output wire          hdmi_out_en,
    inout wire           hdmi_scl,
    inout wire           hdmi_sda,

    input wire           clk,
    input wire           rst_btn, 
    //output wire [9:0]    hdmi_data_out_ch0,
    //output wire [9:0]    hdmi_data_out_ch1,
    //output wire [9:0]    hdmi_data_out_ch2,
    //output wire          PixelClk_out,
    //output wire          pVde,
    //output reg           new_frame,
    //output reg           new_frame_60,
    //output wire          aPixelClkLckd,
    //output wire          all_rdy,
    output wire [5:0]    vga_g,
    output wire [4:0]    vga_b,
    output wire [4:0]    vga_r,
    output wire          vga_hs,
    output wire          vga_vs
    wire [23:0] vid_pData;
    wire vid_pHSync;
    wire vid_pVSync;
    wire ddc_sda_i;
    wire ddc_sda_o;
    wire ddc_sda_t;
    wire ddc_scl_i;
    wire ddc_scl_o;
    wire ddc_scl_t;
        .DDC_SCL_O (ddc_scl_o),

    IOBUF IOBUF_hdmi_scl
    IOBUF IOBUF_hdmi_sda

    assign vga_g = vid_pData[7:2];
    assign vga_b = vid_pData[15:11];
    assign vga_r = vid_pData[23:19];
    assign vga_hs = vid_pHSync;
    assign vga_vs = vid_pVSync;

    assign hdmi_hpd = 1'b1;
    assign hdmi_out_en = 1'b0;
    reg last_vsync;
    always @(posedge PixelClk_out)
        last_vsync <= vid_pVSync;
        if (vid_pVSync == 1'b1 && last_vsync == 1'b0) begin
            new_frame <= 1'b1;
        else begin
            new_frame <= 1'b0;
    reg [5:0] temp;
    always @(posedge PixelClk_out)
    if(rst_btn == 1'b1)
        temp <= 6'd0;
        new_frame_60 <= 1'b0;
        if(new_frame == 1'b1)
            temp <= temp + 1'b1;
        if(temp == 6'd59)
            temp <= 6'd0;
            new_frame_60 <= ~new_frame_60;

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I've got some places you could start looking:

1) Are you providing refclk as 200MHz?

2) Are kIDLY_TapValuePs and kIDLY_TapWidth being left as default values? I've never seen them before so I'm assuming they should be left as defaults.

3) You could try registering the sync signals and data signals right before they are sent to the VGA. This could clean them up a bit. Probably won't affect quality so much though.

4) Is your design meeting timing?

5) You could try using kClkRange=1.

6) Try a different monitor and see if this changes the quality. This can help determine if the issue is on the decode side or the output side. You can also try messing with the monitor's timing settings to see if that affects quality. 

7) Try a different input source. Some input sources work better than others with this IP core.

If none of these things seem to help, please provide more information about how the quality is degrading. Is it blurry edges? jittery? Using test patterns on the input can help determine what is degrading exactly.

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Hey there!

For the standard I/O pins on 7-series FPGA are only rated to 1250 Mb/s or 950Gb/s depending on speed grade, so pixel clocks > 125MHz are very much out of spec.

Also the ability to tune the capture phase (using IDELAY2 primitive) does not have enough resolution align clock edges at 148.6MHz pixel clocks, so it is somewhat hit and miss.

However, If you use the high speed transceivers for HDMI, anything is possible :-)

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