hi - i have an issue i just cannot find the answer for.
i have a working design. the design takes the output of a relay as input in the real world.
however, for development purposes i have a test mode that muxes a dummy input to my system from a block generating pseudo random sequences off an LFSR.
i have tried to add the real world input as coming in from JA[0], so i have uncommented the lines in my constraints file:
set_property PACKAGE_PIN B13 [get_ports {mysensor}]
set_property IOSTANDARD LVCMOS33 [get_ports {mysensor}]
mysensor is the single bit input name on my top level design VHDL entity
the original lines were commented out:
#set_property PACKAGE_PIN B13 [get_ports {JA[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
but i get DRC errors and the flow falls over before bitgen
there is a suggested work around to relax the pin location constraint but i'm reluctant to try it.
can anyone help here? is there some other place where i need to say i want this input?
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logicmonkey
hi - i have an issue i just cannot find the answer for.
i have a working design. the design takes the output of a relay as input in the real world.
however, for development purposes i have a test mode that muxes a dummy input to my system from a block generating pseudo random sequences off an LFSR.
i have tried to add the real world input as coming in from JA[0], so i have uncommented the lines in my constraints file:
set_property PACKAGE_PIN B13 [get_ports {mysensor}] set_property IOSTANDARD LVCMOS33 [get_ports {mysensor}] mysensor is the single bit input name on my top level design VHDL entity the original lines were commented out: #set_property PACKAGE_PIN B13 [get_ports {JA[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
but i get DRC errors and the flow falls over before bitgen
there is a suggested work around to relax the pin location constraint but i'm reluctant to try it.
can anyone help here? is there some other place where i need to say i want this input?
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