Do you have an example of a VHDL digital filter to filter noise?

[cristian_zanetti]

Hello, I am using a NEXYS 4 DDR and I am acquiring some data with the ADC that has this card, I want to implement a filter to eliminate the noise. Someone has an example in VHDL. Thank you.

[jpeyron]

Hi @cristian_zanetti,

Here is a forum thread that discusses noise on the xadc of the basys 3(artix 7) and some different options on how to deal with it. Here is a VHDL project done by @hamster that has averaging enabled and set to 16. You can go as high as 256. Have you tried using averaging to eliminate the noise?

cheers,

Jon 

[cristian_zanetti]

Thanks for answering. If I used the average of the ADC. However, it is urgent to implement a filter, for example the filter that eliminates the frequencies of 60 hz magnetic field in VHDL.

[D@n]

@cristian_zanetti,

Some time ago, I put together two tutorial type discussions describing some straight-forward filters that you can make on an FPGA.  While the examples are all in Verilog, you might find that the discussion applies to both VHDL and Verilog.

You can find the first post here.  It discusses both a two-tap FIR filter as well as a recursive IIR averager.

The second post is here.  It discusses how to create a very generic FIR filter that can run at your FPGA's full speed.  I'm likely going to follow this up with a simpler version of the same, but I've got some other posts to work through first in order to get there.

I'm still hoping to put further tutorials together--describing half-band filters, hilbert transforms, filters applied to slower signals, upsamplers, and downsamplers, etc.  I just haven't gotten that far (yet).

Depending on the quality of 60 Hz rejection filter that you want, you may find that one minus a two pole 60Hz bandpass IIR filter will work quite well for your operation.  It's crude, but cheap.  If you decide that you need better quality, then ... you may wish to return to an FIR filter where you can control the phase response.

Dan

[Piasa]

What does the entire system look like?  DSP applications are much easier to implement on a computer.  If the ADC is low-rate data, a CPU/GPU implementation might be much easier to do and also has the advantage of using floating point math.

If the ADC is multichannel, you might consider adding a second ADC input that can be used as a noise reference.  This can be used with and adaptive filter to remove the noise.  If the sampling rate is fairly low, this could be done on the FPGA with normal adaptive filtering methods.  The concept is that the spectral content of the noise reference is correlated to the noise in the main channel.  If the data is post processed, you can also remove this from a single recording under some assumptions.

If the fpga is to be used and the sampling rate is low, it still makes sense to serialize the operations for the filter to reduce resources.  This can be done in different ways.  The DSP48 slices and BRAMs can be used together to create a mini-dsp that executes a simple set of instructions.  This is actually easier than it sounds as there doesn't need to be any branching or anything that is difficult in a normal CPU.  Software pipelining is also easy to do.  This is easier to do in VHDL, or with a script that generates the RTL for this application.

[Van Loi LE]

16 hours ago, cristian_zanetti said:

Thanks for answering. If I used the average of the ADC. However, it is urgent to implement a filter, for example the filter that eliminates the frequencies of 60 hz magnetic field in VHDL.

Did you take a look at this VHDL Filter for ECG Denoising? It gives you a VHDL code and testbench for a low-pass FIR filter for denoising.