Arty with custom IP

[jello_cat]

I have Arty A7-35T and I tried following this tutorial (http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html) to have the Microblaze communicate with custom VHDL. In the C++ file the macro for 'XPAR_MY_MULTIPLIER_0_S00_AXI_BASEADDR' matches what the address editor says. I always 0 from the address that should be the result of the multiplier. I don't know what I'm doing wrong or if anything from the tutorial needs to be done different for the Microblaze.

[jpeyron]

Hi @jello_cat,

Here is our Creating a Custom IP core using the IP Integrator for the Zybo(zynq). Can you give us screen shots of what is going on so we can better assist you. 

cheers,

Jon 

[jello_cat]

I'm trying to do a project where the Microblaze processor will do a tiny bit of communication with a much larger custom VHDL design. I was trying to get this working as a proof of concept that the Microblaze can communicate to custom VHDL. My block diagram is as follows:

 

The custom multiplier code multiplier_0.vhd my_multiplier_v1_0_S00_AXI.vhd and the IP that I made following the tutorial

It seems like I have the wrong address set up for the output of the multiplier because when I run it I do not get a valid result. (First test 0x00020003 was input and second test 0x00020006 was input)

 

[jpeyron]

Hi @jello_cat,

Here is a forum thread that does our custom ip creator tutorial in VHDL,  I have not seen anything wrong with your HDL.  I will look into this further next week. Another way to get custom HDL code to work with the Microblaze axi system you can use the add a block feature in Vivado 2016.x and up connected to the AXI GPIO. Here is a forum thread that describes how to accomplish this.

cheers,

Jon