takieddine Posted September 21, 2017 Share Posted September 21, 2017 Hi, Could you please explain how the read and write batches are used in the frame buffer controller ? Link to comment Share on other sites More sharing options...
jpeyron Posted September 21, 2017 Share Posted September 21, 2017 Hi @takieddine, I downloaded the VmodCAM_Ref_HD Demo_12 form here. Looking at the VHDL code which can be found here: VmodCAM_Ref_HD Demo_12\VmodCAM_Ref_HD\FBCtl.vhd the file description states that the FBCtl is a frame buffer controller using a DDR2 memory for physical storage. The controller allocates two separate frame buffers each one with a stream write FIFO interface for video sources and one stream read only port for a video consumer. MSEL_I configures the read port to stream data from either frame buffer. The VHDL code has good comments to describe what is going on in each code block. There is a more generic description of the project in the readme.txt in the project as well. Could you be more specific about what part of the FBCtl.vhd you would like explained. I have also reached out to my co-workers to see if they have any input for you. cheers, Jon Link to comment Share on other sites More sharing options...
takieddine Posted September 25, 2017 Author Share Posted September 25, 2017 Hi Jon, I have three questions about the reference VGA design, how do you select the size of the read and write batches ? constant RD_BATCH : natural := 16; constant WR_BATCH : natural := 32; How do you choose the ending address in the frame memory buffer controller ? in the given code we have if (pc_rd_addr1 = 640*2*480/(RD_BATCH*4)-1) then pc_rd_addr1 <= 0; And why do you convert to p3_cmd_pr_addr like this p3_cmd_byte_addr <= conv_std_logic_vector(pc_rd_addr1 * (RD_BATCH*4),30) Link to comment Share on other sites More sharing options...
jpeyron Posted September 25, 2017 Share Posted September 25, 2017 Hi @takieddine, I have reached out to the creator of the project to get input about your question. Unfortunately they are away from the office. It might be up to 2 weeks before they are able to respond to this thread. I am very sorry about the inconvenience. Thank you, Jon Link to comment Share on other sites More sharing options...
Cristian.Fatu Posted September 26, 2017 Share Posted September 26, 2017 Hello, Hoping that this might help you, I am sending you a demo application. It is a 3D Vision demo, based on VmdoCAM. Please note that this demo was not released, so it is not "polished". https://www.dropbox.com/s/zoyo4ja8cbgzv2j/3D Camera Demo Project.zip?dl=0. Good luck! Link to comment Share on other sites More sharing options...
takieddine Posted September 26, 2017 Author Share Posted September 26, 2017 Thank you Cristian, In the documentation it is mentioned that this project applies to rev D of the board, I have REV C can I use it ? Link to comment Share on other sites More sharing options...
Cristian.Fatu Posted September 26, 2017 Share Posted September 26, 2017 Yes, it is stereo vision implementation. Please read the documentation inside the zip file to find more, as I know very few about this project. Link to comment Share on other sites More sharing options...
Cristian.Fatu Posted September 27, 2017 Share Posted September 27, 2017 The last version of VmodCAM is rev. C. Anyway, this example is the only one we have, so try to use it "as it is". When you add new questions, please add new posts, as editing the previous posts is not a good approach because existing answers seem to "float" over replaced questions. Link to comment Share on other sites More sharing options...
takieddine Posted September 27, 2017 Author Share Posted September 27, 2017 I read spartan 6 memory controller documentation, and I understood that the batches sizes are chosen according to the size of the FIFOs inside the memory wrapper; my question now can I use small BRAM FIFOs to buffer the video feeds from VmodCam, lets say I use size of 32 for both batches. Link to comment Share on other sites More sharing options...
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takieddine
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Could you please explain how the read and write batches are used in the frame buffer controller ?
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