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Vmodcam project's read and write batches


takieddine

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Hi @takieddine,

I downloaded the VmodCAM_Ref_HD Demo_12 form here. Looking at the VHDL code which can be found here: VmodCAM_Ref_HD Demo_12\VmodCAM_Ref_HD\FBCtl.vhd the file description states that the FBCtl is a frame buffer controller using a DDR2 memory for physical storage. The controller allocates two separate frame buffers each one with a stream write FIFO interface for video sources and one stream read only port for a video consumer. MSEL_I configures the read port to stream data from either frame buffer. The VHDL code has good comments to describe what is going on in each code block. There is a more generic description of the project in the readme.txt in the project as well. Could you be more specific about what part of the FBCtl.vhd you would like explained.  I have also reached out to my co-workers to see if they have any input for you.  

cheers,

Jon

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Hi Jon,

I have three questions about the reference VGA  design, how do you select the size of the read and write batches ? 

constant RD_BATCH : natural := 16;
	constant WR_BATCH : natural := 32;

How do you choose the ending address in the frame memory buffer controller ? in the given code we have

if (pc_rd_addr1 = 640*2*480/(RD_BATCH*4)-1) then
					pc_rd_addr1 <= 0;

And why do you convert to p3_cmd_pr_addr like this 

p3_cmd_byte_addr <=
        conv_std_logic_vector(pc_rd_addr1 * (RD_BATCH*4),30) 

 

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I read spartan 6 memory controller documentation, and I understood that the batches sizes are chosen according to the size of the FIFOs inside the memory wrapper; my question now can I use small BRAM FIFOs to buffer the video feeds from VmodCam, lets say I use size of 32 for both batches.

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