have read previous postings, none of them answered my problem.
I am using an Arty Z7 20, Vivado 2017.2 and latest board files (A.0).
I have walked through the Zybo getting started with Zynq tutorial, using the Arty Z7 board settings. My block design contains Z7 PS, PS reset, AXI Interconnect and AXI GPIO (btns_4bits).
Block design validates ok and can create HDL wrapper, create bitstream, export hardware and launch the SDK.
I've selected the "Hello World" example and am trying to get it running.
The cable appears to be connected ok and JP4 is set to QSPI.
I am getting the error "Memory write error at 0x100000. APB AP transaction error, DAP status f0000021" when I attempt to run the project.
The memory map suggests this is DDR related. Any ideas on how to proceed?
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Stephen D
Hi all,
have read previous postings, none of them answered my problem.
I am using an Arty Z7 20, Vivado 2017.2 and latest board files (A.0).
I have walked through the Zybo getting started with Zynq tutorial, using the Arty Z7 board settings. My block design contains Z7 PS, PS reset, AXI Interconnect and AXI GPIO (btns_4bits).
Block design validates ok and can create HDL wrapper, create bitstream, export hardware and launch the SDK.
I've selected the "Hello World" example and am trying to get it running.
The cable appears to be connected ok and JP4 is set to QSPI.
I am getting the error "Memory write error at 0x100000. APB AP transaction error, DAP status f0000021" when I attempt to run the project.
The memory map suggests this is DDR related. Any ideas on how to proceed?
Regards,
Stephen
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