VFBC max clock frequency for Atlys

[chcollin]

Hi everyone,

I've been reading Xilinx's DS643 pdf on MPMC configuration (v6.06.a).
Table 91 page 170 lists the maximum frequency that can be used for the VFBC interface clocks, VFBC_Cmd_Clk, VFBC_Wd_Clk and VFBC_Rd_Clk.
Only Spartan-3A DSP, Virtex-4 and Virtex-5 devices are listed.

Where can I find the maximum frequency that can be used to clock VFBC on Atlys spartan-6 ?

Thanx a lot, cheers.

 

[jpeyron]

HI @chcollin,

I have not been able to find any additional information that would help to find the maximum frequency that can be used for the VFBC interface clocks for the Spartan 6.  My co-worker that responded to your Atlys HDMI demo questions is out of the office for a week so would not be able to give any input to this thread until later next week. I would also suggest reaching out to Xilinx about this as well here.

cheers,

Jon

[chcollin]

Thx @jpeyron, i'm going to ask Xilinx as you advice.
I'll post back here if I ever get any answer from Xilinx.

Cheers