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Unstable data received from HDMI/DVI to RGB converter


tuan

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Dear all

I need to make a 1080p60Hz SDI to RGB system, then sending the RGB data to PC via Ethernet.

I use a SDI to HDMI converter and ZYBO board to do so.

On ZYBO board, I used Xilinx DVI Receiver (SelectIO Interface as shown in the attached image) IP to receive TMDS signal before decoding to RGB image and write it to 2nd half of DDR memory (256MB from address 1000_0000).

Xilibus core and the corresponding provided embedded linux are used for other control (SD card, Ethernet) and communication. OS is located in the first half of the DDR memory (256MB from address 0000_0000) and is able to read RGB data from the second half.

Since the Zynq 7000 FPGA supports up to 600MHz IO, which is lower than the frequency used for HDMI 1080p60Hz (742.5MHz), I use a SDI to HDMI converter with ability to change frequency from 60Hz to 30Hz so that I can receive 1080p30Hz HDMI as input to the FPGA. OS will read images from 2nd half of memory and send to Ethernet when necessary.

My system works now but I face the instability problem, that is:

- Received image is slightly different with the original one (this issue may related to the converter and/or the verification system), hence I emphasis to the stability here.

- Received images are stable at 720p60Hz (DVI clock is 74.25MHz and serial clock is 371.25MHz), that is there is no different among those images themselves when still image is given to HDMI input. However, when the HDMI input is 1080p30Hz (same DVI and serial clocks as above), there are some different pixels in the blue channel among the received images themselves, especially at the left edge. There is no different in the green and red channel among the received images on my design. Verification (using 3rd party devices) on the SDI and HDMI of the converter shows that the images at SDI and HDMI ports are stable. It means that the instability occurs in my design on FPGA. Report Timing Summary shows that there are some no input/output delay to some ports, setup time violation on xilibus core and reset signal from PS as shown in the attached figures.

Clock setting:

- ARM PLL: 650MHz

- DDR PLL: 525MHz

- Clock to my modules for AXI bus control (write to DDR) and other operations: 200MHz

- "set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_out1_dvi_dec_clk_wiz_0_0]" and vise versa are used.

Do you have any idea on the instability problem, suggestions for a solution as well as timing constrain I should use ?

Best regards,

Anh Tuan Hoang

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@tuan,

Fix the async group timing issues by adding clock-domain crossing circuits with false path constraints. That alone might solve the intra-clock issues.

I imagine the Clocking Wizard has 74.25 for input and outputting 1x and 5x. Make sure the clock constraints are correctly generated.

I don't know how the SelectIO interface wizard works, but DVI input requires phase delay calibration, which needs IDELAYCTRL, which needs a 200MHz reference clock. I don't see that anywhere.

Try our IP offering (https://github.com/Digilent/vivado-library/tree/master/ip/dvi2rgb), see if it works any better. Our IP has an internal register (eye_count) that you can debug with ILA to see the results of the phase delay calibration for each channel. Blue having a shorter eye width might explain the issues you are seeing.

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