• 0
chcollin

My noobish questions on Atlys HDMI demo

Question

Hi FPGA Gurus !

This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! šŸ˜ƒ

Question 1 (solved):

I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads :
/*
Ā * These constants refer to the configuration of the hdmi_out core parameters.
Ā */
#define pFrame 0x49000000 //frame base address
#define xcoFrameMax 1280Ā  //frame width
#define ycoFrameMax 720Ā Ā  //frame height
#define lLineStride 0x800Ā  //line stride

Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000.
If I look at the MPMC configuration, its base address parameter is set to 0x48000000.
I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ?

Question 2Ā (pending):

The output signal is 1280x720 with a pixel clock at 75 MHz which is not fully HDMI compliant.
Some receivers get along with this signal but some unfortunately don't.
To get a "true" 720p signal, pixel clock should be 74.25 MHz.
Is there any way I could modify the clock generator to get this 74.25 MHz clock signal ?Ā 

Thank you very much for your help

Edited by chcollin

Share this post


Link to post
Share on other sites

Recommended Posts

  • 0

OK, for the 74.25 MHz problem, I think I am going to use a custom DCM core, with clock input @100 MHz

Master DCM will do x11/16
Slave DCM will do x27/25

This should give me exactly 74.25 MHz as output.

Share this post


Link to post
Share on other sites
  • 0

Thank you @[email protected],

The problem was not as difficult as I thought, as we say in french : the problem mostly resides between the seat and the keyboard :)
The fact that I am not in the eletronics nor the FPGA thing makes it sometimes difficult to me to understand how things work.

I finaly endend up adding another clock to the clock generator and modified PLL module configuration.

Reference clock is 100MHz and clock wizard allowed me to add a 22.5MHz clock to the system.
This 22.5MHz clock feeds a PLL module with multiply factor set to 33, which gives me exactly 742.5MHz.
The PLL module outputs 3 clocks :

  • CLK0 with divide factor set to 1 for pxlclk_x10
  • CLK1 with divide factor set to 10 for pxlclk (74.25MHz, 720p specs freq)
  • CLK2 with divide factor set to 5 for pxlclk_x2

Here is a screenshot of the internal clock schematics :
internalClockSchematics.png.a0d7d84cee5abf4e810d30e7b6389916.png

Bitstream generation fails if I do not deselect "Treat timing closure failure as an error" in Project Options.
A close look using Time Analyzer shows this :

================================================================================
Timing constraint: TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT2 = PERIOD TIMEGRP "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT2" TS_sys_clk_pin * 0.75 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
498357 paths analyzed, 31206 endpoints analyzed, 10 failing endpoints
10 timing errors detected. (10 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 734.895ns.
--------------------------------------------------------------------------------
Slack (setup path): -7.306ns (requirement - (data path - clock path skew + uncertainty))
Source: hdmi_out_0/hdmi_out_0/vfbc_rd_reset_i (FF)
Destination: MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1_0 (FF)
Requirement: 0.135ns
Data Path Delay: 1.405ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Skew: -5.487ns (4.455 - 9.942)
Source Clock: hdmi_out_0_VFBC_OUT_cmd_clk rising at 1319.865ns
Destination Clock: clk_75_0000MHzPLL0 rising at 1320.000ns
Clock Uncertainty: 0.549ns

Clock Uncertainty: 0.549ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.472ns
Phase Error (PE): 0.310ns

Maximum Data Path at Slow Process Corner: hdmi_out_0/hdmi_out_0/vfbc_rd_reset_i to MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X30Y100.BQ Tcko 0.525 hdmi_out_0_VFBC_OUT_rd_reset
hdmi_out_0/hdmi_out_0/vfbc_rd_reset_i
SLICE_X31Y99.C4 net (fanout=1) 0.507 hdmi_out_0_VFBC_OUT_rd_reset
SLICE_X31Y99.CLK Tas 0.373 MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1<0>
MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/RdDataPortIn[0]_MReset_n1_INV_0
MCB_DDR2/MCB_DDR2/VFBC2_INST.vfbc/VFBC1_PIM_NGC/UVFBC/rdfifo_reset_dly1_0
------------------------------------------------- ---------------------------
Total 1.405ns (0.898ns logic, 0.507ns route)
(63.9% logic, 36.1% route)

I guess this is due to the fact hdmi_out clock (now at 74.25MHz) does not align with MPMC clock frequency (600MHz).
I don't know if this really matters... It probably does but I don't know how to solve this.

Anyway, if I deselect the option about timing closure failure, I can generate a bitstream and try it.
The project runs.
Now if I connect the Atlys to a TV, things run smooth.
However, if I connect it to a less tolerant device (such as PC LCD monitor), here is what I get :

Supposedly, the video signal has a pixelclock @74.25MHz, total pixel per frames 1650x750 (h/v front porch, back porch and sync follow the specs).
Does anybody have any hint on why this horizontal shaking (slight but present) ?
I have a Marseille mCable HDMI cable (anti aliasing / upscaler 720p/1080p, many video corrections I wish to use on Atlys output). This device seems very strict on input signal and does not accept my generated signal as input. Obviously there is still something wrong with the TMDS signal generated though output frequency is now specs compliant.

I'd really appreciate if you could give me hints on completing this issue.

Cheers

Ā 

Share this post


Link to post
Share on other sites
  • 0

Hi @[email protected],

Thank you for the interest you show regarding my project.

To sum it up :
This is a Spartan 6 PLB project with Microblaze.
It reads video from hdmi_in andĀ stores it in RAM (after image manipulation) thanks to a Multi Port Memory Controler (MPMC) / Video Frame Buffer Controler PIM (VFBC).
RAM is then read by another VFBC that outputs (supposedly @720p, at least that's what I am trying to do now : getting a pure 720p signal, specs compliant) through hdmi_out module.

It is the MPMC that needs this 600MHz clock for internal use.
From what I have understood, it is supposed to run at 8 times the frequency of the Microblaze.Ā 

Clock generator deliversĀ a 75MHz clock for the Microblaze and a 600MHz clock for the MPMC.
As you may have read earlier, I've haded a 22.5MHz clock to the clock generator that feeds a PLL Module to get 74.25MHz at output (720p spec compliant frequency).

Of course, the easiest thing would be to set clock generator to output a 74.25MHz for the Microblaze and a 594MHz clock for the MPMC...
But Spartan 6 cannot do that (at least Atlys can't).

Now I was wondering :
Would it be possible to use clock generator to output a 22.5MHz clock into a PLL module to get my 74.25MHz clock and then use this clock signal as a clock-in to another PLL module that would generate all clocks for the system ? (x8/8 for the Microblaze and hdmi_out, x8/1 for the MPMC ...).
I really don't know if this would not interfere with all other components of the system -PLB bus etc)...

I might try that.

Share this post


Link to post
Share on other sites
  • 0

OK,

I've been working on this, unsuccessfully šŸ˜¢

This is the design I've built :

1/ Clock generator : one single ouput : 22.5MHz from 100MHz internal clock (a single DCm x9/40 should achieve this but I might be generated somehow else)
2/ PLL module x33 / (1, 10, 5) to get 742.5MHz (pixel_clock_10x), 74.25MHz (pixel_clock + system_clock (PLB bus etc)), 148.50MHz (pixel_clock_2x)
3/ DCM master/slave module (master x11/10 [VCO 247.5MHz, output 24.75MHz], slave x24 /1 [VCO 594MHz, ouput 594MHz]), driving MPMC memory clock

I thought this would go smooth but unfortunatly, I'm facing MPMC clock problems.

First bitstream generation form XPS, I got an error telling me thatĀ C_MPMC_CLK_MEM_2X_PERIOD_PS could not be calculated and was out of range.
After readingĀ MPMC documentationĀ (page 6) :

Clock memory value is calculated automatically based on what is connected to Port MPMC_Clk_Mem_2x in XPS (for example a clock_generator output or a signal/port with MHS tag CLK_FREQ = xxxx.) The value can be overwritten; if set by the user, it is not calculated.

So I decided to modify system.mhs to giveĀ C_MPMC_CLK_MEM_2X_PERIOD_PSĀ the value 1684 ps (which is in the range given in the doc). This value is the period for a 594MHz clock.

However, now I get the following error message :

ERROR:EDK:4061 - INSTANCE: MCB_DDR2, PARAMETER: C_MPMC_CLK_MEM_2X_PERIOD_PS -
   Given value (1684) is incorrect. The expected value is 44444. Please update the value in MHS - /opt/Xilinx/Projects/HDMI_Rotator/project/system.mhs line
   182 
ERROR:EDK:3371 - Conversion to XML failed.
make: *** [SDK/SDK_Export/hw/system.xml] Error 64

I don't know what to do with this error and where this 44444 value is taken from !
Can anybody help, please ?Ā 

Share this post


Link to post
Share on other sites
  • 0

OK, I figured it out, I had to play with the mpd file to explicit input clock freq and clock factor, so that the output frequency could be calculated.
However, this led me to another error : MPMC clock mem seems to be only PLL_ADV compatible ... so my DCM module didn't comply this specification.

Due to the limited number of DCM and PLL on the Atlys board, I finaly decided to review the entire clock design.
I ended up designing this :

1/ Removed the clock_generator_0 module as I didn't know if the module would generate clocks with DCM or PLL or both.
2/ Added a self made clock generator module. It takes at input system clock (100MHz), feeds a CLK_GEN (*9/40) (VCO 900MHz) into a DCM_SP (*11/10) (VCO 247.5MHz) to get one only output clock at 24.75MHz that fits quite well for my needs.
3/ Modified pll_module_0 : input is the 24.75MHz clock defined earlier, mult *30 and three output clocks:

  • /10 to get 74.25MHz for pixel clock and system clock
  • /5 to get pixel clock 2x
  • /1 to get pixel clock 10x

4/ Added another PLL module : input is the 24.75MHz clock defined earlier, mult *23, div /1 to get 594MHz (8 times the system clock) to clock the MPMC Memory clock.

This way, MPMC is clocked by a PLL and I have enough timing resources available on the Atlys to design this.

However, I now am facing another problem !!! (yes...)
It seems there is a constraint problem when generating bitstream.

The error message is the following :

ERROR:Place - ConstraintResolved NO placeable site for
   hdmi_out_0/hdmi_out_0/Inst_dvi_out_native/ioclk_buf
ERROR:Place - ConstraintResolved NO placeable site for
   MCB_DDR2/MCB_DDR2/mpmc_core_0/gen_spartan6_mcb.gen_spartan6_bufpll_mcb.bufpll
   _0
ERROR:Place - SIO has over-constrained componet
   hdmi_out_0/hdmi_out_0/Inst_dvi_out_native/ioclk_buf to have to placeable
   sites. Constraints come from driver constraints AND load IO constraints

I guess this is a constraint problem as I didn't had constraints regarding my "home made" clock generator nor the second PLL module...
For those interested, you can find the clock generator source files and the system.ucf file attached to this post.

If someone can help me solve this new problem, that would be very nice.

Cheers !

system.ucf dcm_720p_v2_1_0.mpd dcm_720p.vhd

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now