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My noobish questions on Atlys HDMI demo


Hi FPGA Gurus !

This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! =)

Question 1:

I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads :
 * These constants refer to the configuration of the hdmi_out core parameters.
#define pFrame 0x49000000 //frame base address
#define xcoFrameMax 1280  //frame width
#define ycoFrameMax 720   //frame height
#define lLineStride 0x800  //line stride

Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000.
If I look at the MPMC configuration, its base address parameter is set to 0x48000000.
I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ?

Thank you very much for your help

Edited by chcollin

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0x48000000 is the start of the DDR2 memory address. The next 128 MB of address space are the entire contents of the DDR2 memory on the Atlys. The program (hdmi_demo) is actually executing from the front of the DDR2 (0x48000000). So, assuming the program is not larger than 16MB, 0x49000000 is a safe physical address within the DDR2 that should not overlap with the program's memory. 

This was poor style to assign the address this way for many reasons. It would have been better to just declare an array of bytes big enough to contain the frame buffer, and then dereference the array to get the physical address.

0xD1000000 is the base address of the hdmi_out core's register map for controlling that IP core

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Thank you very much @sbobrowicz, your explanation makes it a lot clearer to me. Especially the offset from the DDR starting address so that the code can be safely stored without overlapping data.

However, I might disagree about the 0xD1000000 value, or my comprehension is completely mistaken (which is highly possible as I really am beginner)
Looking at project/pcores/hdmi_out_v1_00_a/hdl/vhdl/hdmi_out.vhd, we can see that :
constant vfbc_cmd1 : std_logic_vector(31 downto 0) := "0" & FRAME_BASE_ADDR(30 downto 7) & "0000000"; --Frame base address must be 128 byte alligned and MSB used as WNR

File ./project/pcores/hdmi_out_v1_00_a/data/hdmi_out_v2_1_0.mpd reads :
PARAMETER FRAME_BASE_ADDR = 0x00000000, DT = std_logic_vector, ASSIGNMENT = REQUIRE, DESC="FRAME BASE ADDRESS", LONG_DESC="Select the physical address of the framebuffer in memory. This address must be 128 byte alligned (bits 6-0=0) and designate a region within the MPMC space large enough for the frame.

And finaly, in ./project/system.mhs, the paramater is set : 

So, to my comprehension, 0xD1000000 is the very address in memory from which the hdmi_out vfbc pim reads the frame.

However bit 31 is excluded  in the address used in vfbc_cmd1, so 0xD1000000 "turns into" 0x51000000.
It's getting closer :) ... yet not 0x4900000 !

 Where am I mistaken ?

Edited by chcollin

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Wow, its been a long time since working with the MPMC, I forgot how much differently that works than the more modern MIG+VDMA solution.

You are right, the 0xD1000000 Address is not the register map address assigned by EDK. It is the Physical address of the DDR that the MPMC will write the video data to. I forgot that this had to be set in EDK before building the bitstream (VDMA lets you set it in software from SDK). 

So here is the magic part: since the MPMC knows that there is only 128 MB, it seems to be automatically masking out any unnecessary bits. So it is effectively only looking at bits (26 downto 7), and 0xD1000000 turns into 0x01000000. Note that providing 0x49000000 would also get masked down to 0x01000000 which is why the software works. So you can effectively think of the value that you provide to FRAME_BASE_ADDR as a relative address within the DDR physical address space.

Note that the above explanation heavily relies on the base address of the MPMC being 128MB aligned (so bits 26 downto 0 are all '0'). In this design, the MPMC is given address 0x48000000, which satisfies this requirement. I honestly have no idea how the FRAME_BASE_ADDR value will be interpreted if the MPMC were assigned a base address that is not aligned to 128 MB.

I have no idea why the project sets the FRAME_BASE_ADDR to 0xD1000000 instead of 0x49000000, or even 0x01000000. My bet is that an earlier version of the project had the MPMC base address set to 0xD1000000, but this was changed when it got updated at some point. Since nothing broke, it slipped through unnoticed. 

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