This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! ?
Question 1 (solved):
I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads : /*
* These constants refer to the configuration of the hdmi_out core parameters.
*/
#define pFrame 0x49000000 //frame base address
#define xcoFrameMax 1280 //frame width
#define ycoFrameMax 720 //frame height
#define lLineStride 0x800 //line stride
Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000.
If I look at the MPMC configuration, its base address parameter is set to 0x48000000.
I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ?
Question 2 (pending):
The output signal is 1280x720 with a pixel clock at 75 MHz which is not fully HDMI compliant.
Some receivers get along with this signal but some unfortunately don't.
To get a "true" 720p signal, pixel clock should be 74.25 MHz.
Is there any way I could modify the clock generator to get this 74.25 MHz clock signal ?
Question
chcollin
Hi FPGA Gurus !
This thread is dedicated to the (probably numerous) questions I might have about the Atlys HDMI demo. It will be edited each time a question is answered or another question pops up ! ?
Question 1 (solved):
I dont understand the calculation of the Frame Base Address in hdmi_demo.h. The code reads :
/*
* These constants refer to the configuration of the hdmi_out core parameters.
*/
#define pFrame 0x49000000 //frame base address
#define xcoFrameMax 1280 //frame width
#define ycoFrameMax 720 //frame height
#define lLineStride 0x800 //line stride
Now, if I look at the hdmi_out core, i'm ok about frame width and height and also about the line stride. However, the core FRAME BASE ADDRESS parameter is set to 0xD1000000.
If I look at the MPMC configuration, its base address parameter is set to 0x48000000.
I'm a bit confused. Could someone explain how this 0x49000000 value is obtained out of 0x48000000 and 0xD1000000 ?
Question 2 (pending):
The output signal is 1280x720 with a pixel clock at 75 MHz which is not fully HDMI compliant.
Some receivers get along with this signal but some unfortunately don't.
To get a "true" 720p signal, pixel clock should be 74.25 MHz.
Is there any way I could modify the clock generator to get this 74.25 MHz clock signal ?
Thank you very much for your help
Link to comment
Share on other sites
32 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.