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cnun999

Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings

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I have designed a adaptive  audio deniosing filter using system generator later on iam  try to synthesis this design in vivado from last 36 hours but synthesis not completed . i got info in log as "Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings"  please any body help regard this..................

 

thanking you

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@cnun999,

Looks like you posted on the Xilinx forum as well.  No response, huh?

Sadly, you haven't provided enough information for anyone to solve your problem.  You've offered no code, and haven't found any offending line.  The fact that it's running for 36 hours means there's a problem, but you might need to break the problem down before help will make sense.

Normally, I'd tell any Verilog designers to run their design through Verilator with the "-Wall" option.  This is fast, and finds most of my errors.  However, you appear to be using system generator so Verilator is not likely to be an appropriate option.

So, let's start at the top: What chip and/or board are you using?  Can you post your code?  Can you remove one item (or more) from your code and get it to build successfully?  That can often help find the one item (or more) that's the problem.  We can then focus on that one item.

Not sure if I'll be able to help, but ... this should be a good start.

Dan

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The synthesis not completed might be unrelated.  This specific "warning" is one of the annoying "optimizations are warnings" cases.  This might come up if you have an incorrect clock/reset configuration, unconnected outputs, or constant inputs in some cases

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15 hours ago, D@n said:

@cnun999,

Looks like you posted on the Xilinx forum as well.  No response, huh?

Sadly, you haven't provided enough information for anyone to solve your problem.  You've offered no code, and haven't found any offending line.  The fact that it's running for 36 hours means there's a problem, but you might need to break the problem down before help will make sense.

Normally, I'd tell any Verilog designers to run their design through Verilator with the "-Wall" option.  This is fast, and finds most of my errors.  However, you appear to be using system generator so Verilator is not likely to be an appropriate option.

So, let's start at the top: What chip and/or board are you using?  Can you post your code?  Can you remove one item (or more) from your code and get it to build successfully?  That can often help find the one item (or more) that's the problem.  We can then focus on that one item.

Not sure if I'll be able to help, but ... this should be a good start.

Dan

thank you for your suggestion, I can't share the design because project work . Iam using Virtex-7 VC709 Evaluation Platform (xc7vx690tffg1761-2) board

 

 

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@cnun999,

Well, if you can't share your code, then there's not much I can do to fix it.  Sorry.

You might find it valuable though to take pieces out of it, and see if that helps you narrow down the problem--but I'm repeating myself to say this at this point.

You might also considering entering into a contract arrangement with a more experienced designer, working some non-disclosure agreements through the legal team, and trying again.  I'd offer my services to that end but ... I don't use system designer much.  So, again, I'm sorry I can't be of much more help.

Dan

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