ZYBO Port Names Problem

[swimteam]

Implementing a AXI_GPIO gives a choice of the leds, buttons, switches or custom. For example, I select leds and everything is fine. However, when I select CUSTOM the port name is "gpio" or something like that shows up. I then have a commented out Master Constraint file and un-comment the "leds" and rename them to "gpio" same as in the block diagram. It fails place & route.

The Zyno board was selected during the create project phase. It seems to me that if I have a constraint file - then that would override the other constraints (whereever they may be) that are being used. That's not what is happening.

Anyone know why?

My goal is to control the PORT names. I would like to name the ports to whatever and use a constraint file to assign the pin to that port.
 

[Notarobot]

Hi, @swimteam

It would be great if you show you design and constraints file changes. I assume that you are using default ZYBO_Master.xdc constraints file.

Now where do you want to route your custom GPIO signals?

[Piasa]

Can you post any relevant error messages as well?  It is almost always better to post any error messages as well as tool versions.

[Rainer]

You can set the port name in the external interface properties.

For a custom I/O, Vivado instantiates tristate buffers (IOBUF) in your HDL wrapper.

For the constraints, you can look up the pin name of the tristate signal in the HDL wrapper.