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Hello,

I'm having trouble understanding how to address the J6 header on the Arty board. I've been able to interact with the GPIO registers to toggle other ChipKit shield pins as well as toggle all of the led's. When generating the project, I see that the base address for SPI in my project is at 0x44a00000 with high address being 0x44a0FFFF. I don't understand where in that memory the J6 header is, and am unable to find any resources with the answer. It might also be good to note that I generated the IP block by dragging and dropping the "SPI connector J6" from the Board section of the IP design.  I've looked into the implemented design and see that the spi_io0_io, spi_io1_io, spi_ss_io, and spi_sck_io are connected correctly according to the arty schematic, I'm just unsure how to do SPI transfers over these pins (my logic analyzer doesn't show any activity when doing transfers).

 

Regards,

Nystflame

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Hi @Nystflame,

I have been looking into your question about the J6 SPI connector this afternoon. I will be working on this more tomorrow. On a side note, I have used the MTDS on the Arty and it uses the J6 connector. I would also suggest to look at the Pmod IP core for the MTDS here.  If you haven't used our Pmod IP cores and are interested at looking at this example then this tutorial will help with setting up the block design.

cheers,

Jon

Edited by jpeyron
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Hi @Nystflame,

We do not have completed sdk code to run the J6 SPI connector in general. We have one IP core that uses the J6 spi connector which is the PmodMDTS. I took some spi code from one of our other IP cores. I have attached my spi J6 project below. The sdk code should be close to what you need. The PmodMTDS I mentioned earlier communicates through either the J6 spi connector or through a pmod so its sdk code is much more complicated. You can get more information about the axi quad spi ip core if you right click on the axi quad spi IP you can click on IP documentation and then click on view product guide. This guide should also help to fine tune the sdk code in my project.

cheers,

Jon

Arty_j6.zip

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On 8/31/2017 at 3:31 PM, jpeyron said:

Hi @Nystflame,

We do not have completed sdk code to run the J6 SPI connector in general. We have one IP core that uses the J6 spi connector which is the PmodMDTS. I took some spi code from one of our other IP cores. I have attached my spi J6 project below. The sdk code should be close to what you need. The PmodMTDS I mentioned earlier communicates through either the J6 spi connector or through a pmod so its sdk code is much more complicated. You can get more information about the axi quad spi ip core if you right click on the axi quad spi IP you can click on IP documentation and then click on view product guide. This guide should also help to fine tune the sdk code in my project.

cheers,

Jon

Arty_j6.zip

@jpeyron ,

Thanks for the info! I also managed to get the j6 header working... I hadn't made the correct pins external in the block designer and created the appropriate constraints file to attach the external pins to the physical pins on the header.

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