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macgyverque

Multiple UARTLite Instantiation w/ Microblaze

Question

Trying to instantiate multiple UARTLite cores in a microblaze design using an Arty Board. For some reason, the output of both UARTLite modules is going through the same USB UART port as opposed to the second port I've configured. 
 
Any suggestions?
 
[CONSTRAINTS]
set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_txd]
set_property PACKAGE_PIN U11 [get_ports usb_uart_bc127_txd]
set_property PACKAGE_PIN V16 [get_ports usb_uart_bc127_rxd]
 
 
[SOURCE CODE]
#include "xparameters.h"
#include "xstatus.h"
#include "xuartlite.h"
#include "xil_printf.h"
 
/************************** Constant Definitions *****************************/
#define UARTLITE_DEVICE_ID_0 XPAR_UARTLITE_0_DEVICE_ID
#define UARTLITE_DEVICE_ID_1 XPAR_UARTLITE_1_DEVICE_ID
#define TEST_BUFFER_SIZE 16
int UartLitePolledExample(u16 DeviceId);
 
/************************** Variable Definitions *****************************/
XUartLite UartLite_0; /* Instance of the UartLite Device */
XUartLite UartLite_1; /* Instance of the UartLite Device */
/*
* The following buffers are used in this example to send and receive data
* with the UartLite.
*/
u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */
u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */
int main(void) {
int Status;
/*
* Run the UartLite polled example, specify the Device ID that is
* generated in xparameters.h
*/
Status = XUartLite_Initialize(&UartLite_0, UARTLITE_DEVICE_ID_0);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (Status != XST_SUCCESS) {
xil_printf("Uartlite polled Example Failed\r\n");
return XST_FAILURE;
}
Status = XUartLite_Initialize(&UartLite_1, UARTLITE_DEVICE_ID_1);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (Status != XST_SUCCESS) {
xil_printf("Uartlite polled Example Failed\r\n");
return XST_FAILURE;
}
xil_printf("Successfully ran Uartlite polled Example\r\n");
//XUartLite_Send(&UartLite_0, SendBuffer, TEST_BUFFER_SIZE);
int temp = 80000;
int simplecounter = 0;
char links[] = "DIGILENT DIGILENT\n\0";
char linksx[] = "ARTY ARTY ARTY ARTY\n\0";
while (1) {
if (1) {
xil_printf("Cha Cha Cha.... %d\r\n", simplecounter++);
XUartLite_Send(&UartLite_0, &links, TEST_BUFFER_SIZE);
XUartLite_Send(&UartLite_1, &linksx, TEST_BUFFER_SIZE);
temp = 80000;
}
}
return XST_SUCCESS;
}
 
[XPARAMETERS]
/* Definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_AXI_UARTLITE_0_DEVICE_ID 0
#define XPAR_AXI_UARTLITE_0_BAUDRATE 9600
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_0_DATA_BITS 8

/* Definitions for peripheral AXI_UARTLITE_1 */
#define XPAR_AXI_UARTLITE_1_BASEADDR 0x40610000
#define XPAR_AXI_UARTLITE_1_HIGHADDR 0x4061FFFF
#define XPAR_AXI_UARTLITE_1_DEVICE_ID 1
#define XPAR_AXI_UARTLITE_1_BAUDRATE 9600
#define XPAR_AXI_UARTLITE_1_USE_PARITY 0
#define XPAR_AXI_UARTLITE_1_ODD_PARITY 0
#define XPAR_AXI_UARTLITE_1_DATA_BITS 8

/******************************************************************/
/* Canonical definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
/* Canonical definitions for peripheral AXI_UARTLITE_1 */
#define XPAR_UARTLITE_1_DEVICE_ID XPAR_AXI_UARTLITE_1_DEVICE_ID
#define XPAR_UARTLITE_1_BASEADDR 0x40610000
#define XPAR_UARTLITE_1_HIGHADDR 0x4061FFFF
#define XPAR_UARTLITE_1_BAUDRATE 9600
#define XPAR_UARTLITE_1_USE_PARITY 0
#define XPAR_UARTLITE_1_ODD_PARITY 0
#define XPAR_UARTLITE_1_DATA_BITS 8
 

blockdesign.jpg

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6 answers to this question

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Hi @macgyverque,

I was able to get your sdk code to work in a project that I have attached below. I have attached pictures of how I have connected the rx and tx on the second UART. I attached a screen shot of my block design and of the tera term working along with my AD2 using waveform 2015 showing the uart communication with the chipkit header.

cheers,

Jon

arty_2uarts.zip

uart2_arty.jpg

uart2_arty_2.jpg

arty_uart.zip

Edited by jpeyron

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@jpeyron Thank you so much for your time. I've been questioning the known universe trying to figure out why I can't send data out of a uart which is one of the simplest tasks to accomplish. 

I opened the project you attached last night and it upgraded the majority of the IP modules due to my version of Vivado being newer. I didn't observe the data being output on the TX line using my TTL/UART interface but I'll attribute that to an oversight on my end and will try again this evening and report back.

One observation from your block diagram is that you have separate RX and TX lines coming from your uartlite module while I have what appears to be a port. I think this is a difference in either the version of Vivado or the IP. On the uart_0 IP it's setup to use the usb_uart board definition while the uart_0 IP is setup to use a custom interface. I attached a couple pics to show the delta. 

pic2.jpg

pic.jpg

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Hi @macgyverque,

If you click on the + sign below UART on the IP core it will show rx and tx. I made those pins external instead of the just the uart port to make it more readable. 

cheers,

Jon

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