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Nexys4 DDR: Writing own DDR2 Controller: Correct INTERNAL_VREF voltage?


Hi, I am in the process of developing my own DDR2 controller as an exercise. Consequently, I'm trying to avoid using tools like MIG.

Unfortunately I could not fully escape the clutches of automated tools, as in order to correctly configure the .xdc constraints file, I've had to have a peek at the following .prj file generated by the MIG in the official Digilent DDR2 Demo implementation: https://github.com/Digilent/Nexys-4-DDR-OOB/blob/master/src/ip/ddr/mig.prj

I interpret the following line: "<InternalVref>1</InternalVref>" as setting the INTERNAL_VREF property to 1V. Therefore, I add the following line in my .xdc file:

set_property INTERNAL_VREF 1 [get_iobanks 34]

However, this configuration fails to implement for the Nexys4 DDR chip with the following error:

[DRC 23-20] Rule violation (IVREF-2) INTERNAL_VREF - Bank 34 has INTERNAL_VREF set to an unsupported value (1.000V).  Supported VREF values for this part are:

Which value should I choose to use?

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As to Vref, the place to look is the schematic for your board. It will tell you what Vref for the IO bank connected to the DDR actually is... not that reading the Xilinx documentation is a bad suggestion. The constraints file IOSTANDARD, the schematic termination and IO bank Vref, and the device reference manual information should all be in agreement.

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I applaud your effort. Simulating MIG based designs, even if you are using Verilog, is a pain. The MIG flow is a pain even if all you want to do is tweak a current MIG project.

One thing that every SDRAM or DDR controller, developed by individuals who don't work for an FPGA vendor, that I've seen is missing is the auto-calibration phase, which ideally could be done at any time as the FPGA and DDR die temperatures change.  Actually, anyone who has touched an FPGA board with the DDR operating knows that a good portion of the PCB sees quite a rise in temperature that could impact nearby devices unrelated to the DDR. Of course what's acceptable for playing around work and commercial work are two different things. The good news is that all of the source generated by the MIG tool are available as a guide for getting a clue as to what one needs to be concerned about. It's heavy reading but informative.

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Thank you all for your helpful comments,

Indeed, on page 100 of UG 471: "7 Series SelectIO" I found the following table:


It appears that 0.9V is the VREF configuration that should be used with SSTL18_II (be it INTERNAL or not).

Edited by maximb
specify standard
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@maximb I posted the following a few hours ago and for some reason it disappeared.

The place to see what Vref actually is set to is on the schematic for your board. Hopefully, the Digilent master constraints file, the schematic Vref and DDR termination, and the Xilinx Series 7 documentation all agree.

PS and after posting this my old one appeared like magic... I don't have an explanation...

And then after coming back to this thread the first one disappeared again. Anyone have any ideas about what's going on?

Edited by zygot
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