nexys video board DDR3 Vivado Project

[boyerkg]

Hi All,

I have a Nexys Video board withe the Artix-7 FPGA, and I want to hook up the DDR3 memory.

The constraint file does not have the pin list.  I am also wondering if there is an existing DDR3 project available for this board?

Regards

Keith

[artvvb]

@boyerkg

A number of the projects found on the Nexys Video resource center use the DDR3 memory. However, these are typically Microblaze projects that use the Xilinx Memory Interface Generator IP and the block design workflow, rather than pure-HDL. You may still be able to use these projects to figure out how Xilinx uses the MIG to set up this connection, I am not sure.

Hope this helps,

Arthur

[D@n]

@boyerkg,

Here's the pin list I used.  And ... yes, I am working on a (to become) open source project for the Nexys Video processor ... I just don't have enough support yet to release it.    (That and it's not working yet either ...) 

You should be able to load this file when, during the course of running through the MIG memory configuration, it asks for pins.

Dan

P.S. ... my project *is* pure Verilog

migmem.ucf

[boyerkg]

Dan,

When I get to the point in the MIG generation to select the pins, Vivado gives an error 7.  It simply exits the IP generation. 

The Xilinx forums discuss this issue, but there appears to be no resolution.  Really????

Keith

 

 

[jpeyron]

Hi @boyerkg,

The nexys video looper demo here( made to work with Vivado 2014) uses the ddr3 in VHDL. It also has a xdc file that includes the ddr3.

cheers,

Jon

[D@n]

@jpeyron,

You realize a simple README.md file describing what each project is and what it is supposed to do would go a long way to making your github site more navigable?

Dan

[boyerkg]

Hi Dan and Arthur,

So, what I ended up doing to get a DDR3 test running on the Nexys Video board was to have one of the example designs that had a mig 7 controller for this board generate an example project.  The example project creates a memory traffic controller.  This is a Xilinx generated module/example.

I used that project to update the pin list for the Nexys Video board pins, for everything from the system clock and reset to the compare error output and init calibration complete.

I checked the pin list, and everything seems to be hooked up according to the video board schematic.

However, I am not getting the init calibration complete to go high?

Any ideas?

Keith

[jpeyron]

Hi @boyerkg,

Your other thread looks to be handling your last question. All other responses to this last question should be handled with your other thread here.

cheers,

Jon