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JessPlazas

Is it possible to adjust the number of samples acquired and the sample rate of the Nexys 4 DDR ADC?

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Hi. I would like to know, if it is possible to modify the sampling frequency, the number of samples of the ADC of the card Nexys 4 DDR ?. I know there are modes of use, but these depend on the registers but do not allow manipulation of these parameters. If you can, I would be grateful if you could tell me how it is possible.

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Hi @JessPlazas,

Here is our github xadc project for the Nexys 4DDR. Here is the coresponding tutorial. This is done in Vivado 2016.4.  Once you have opened it you can double click on the xadc wizard and adjust the adc conversion rate along with many other parameters. 

cheers,

Jon

Edited by jpeyron

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Thank you very much for the project. And I see how you can change the sampling frequency and sampling rate. However, I do not see in what record that can be done. Since this is done from an ipCORE, which for now does not interest me.
I would like to know where it can be done within the code, in which register ?. I would appreciate your response.

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Hi @JessPlazas,

In Vivado, you left click on language templates, choose the language(i choose Verilog), select Device Primitive Instantiation, select Artix-7, select Advanced and lastly select Xilinx Analog-to-Digital Converter(XADC).  Here is a Xilinx forum thread that might be helpful. Here is the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide as well.

cheers,

Jon

Artix7_xadc.jpg

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