Creating a Custom IP core using the IP Integrator Tutorial problems

[FarmerJo]

Hi,

I am running through the Creating a Custom IP core using the IP Integrator tutorial using Vivado 2017.2 and have run into a number of problems as follows.

In section 4.1)

Adding the the line,

parameter integer PWM_COUNTER_MAX = 1024,

Causes Vivado to mark the line with the warning, Warning: syntax error near "Integer".

In section 4.2)

Adding the lines,

output wire PWM0,
output wire PWM1,
output wire PWM2,
output wire PWM3,

Causes Vivado to mark the first line with the warning, Warning: syntax error near "wire".

In section 4.3)

Adding the line,

reg [15:0] counter = 0;

Causes Vivado to mark the first line with the warning, Warning: syntax error near "15".

Adding the remainder of this section causes a number of errors reporting that has not been declared.

I have attached the VHDL file that I am working on.

Any ideas why I am getting these issues?

Forgive me as my VHDL is not very good at the moment and the issues I am having are probably only minor.

Regards

FarmerJo

my_pwm_core_v1_0_S00_AXI.vhd

[artvvb]

@FarmerJo

Well, I'm guessing you are coming to VHDL from Verilog, and if I recall correctly, the tutorial expects the user to be writing Verilog, though I could be wrong. These are not the same language and have different syntax. What is called a parameter in Verilog is a generic in VHDL (I am sure there are some slight differences, but my VHDL isn't especially strong). VHDL infers whether something should be equivalent to a wire or reg based on how it is used, rather than in Verilog where you have to call it out specifically.

As for specific fixes, take a look at the code around your PWM_COUNTER_MAX parameter, C_S_AXI_DATA_WIDTH uses the correct VHDL syntax for what the tutorial is having you do here. For your PWM# wires, the port S_AXI_AWREADY uses the typical VHDL single bit output port syntax.

Hope this helps,

Arthur

[artvvb]

To clarify the problem a little more:

The tutorial likely uses Verilog for it's target language. The tutorial hasn't been updated in a while, and likely targets Vivado 2015 or 2014. While the process of creating a custom core hasn't changed much in this time, the tutorial is likely missing a step where you select what language you want to work in that may have been added for Vivado 2017.

I missed the section 4.3 syntax in the first post, take a look at the syntax for axi_bresp for how to translate the counter register to VHDL. The user logic section will also need to be changed to VHDL, or you can just restart the tutorial, and pay particular attention to any dropdown menus that default to a VHDL option, these may not exist, I am still primarily using Vivado 2016 personally, and haven't walked through making a custom IP in that version yet.

[FarmerJo]

Hi artvvb,

Thanks for the replies. Unfortunately I am in the process of learning VHDL and have no experience with Verilog at all. I have carefully read your advice and so far come up with the following code for section 4.3)

-- Add user logic here
-- simple counter
process(S_AXI_ACLK)
variable counter : integer := 0;
begin
  if(rising_edge(S_AXI_ACLK)) then
    if(counter < (PWM_COUNTER_MAX-1)) then
      counter := counter + 1;
    else
      counter := 0;
    end if;
  end if;

-- comparator statements that drive the PWM signal
if(counter < slv_reg0) then PWM0 <= '1'; else PWM0 <= '0'; end if;
if(counter < slv_reg0) then PWM1 <= '1'; else PWM1 <= '0'; end if;
if(counter < slv_reg0) then PWM2 <= '1'; else PWM2 <= '0'; end if;
if(counter < slv_reg0) then PWM3 <= '1'; else PWM3 <= '0'; end if;

end process;

The first part which defines the counter and increments it, is not showing any problems in Vivado (2017.2), however the second part, where PWM0 to PWM3 are assigned is causing an error which I can understand but cannot see how to resolve. The problem to me is that counter is a variable but slv_reg0 (slv_reg1, slv_reg2 and slv_reg3) are signals and the comparison (<) is not compatible.

Any help to resolve this would be appreciated.

My section 4.1 code is as follows.

-- Users to add parameters here
constant PWM_COUNTER_MAX : integer := 1024;
-- User parameters ends

And my section 4.2) code is as follows.

-- Users to add ports here
PWM0 : out bit;
PWM1 : out bit;
PWM2 : out bit;
PWM3 : out bit;
-- User ports ends

Please advise if there appears to be a problem here.

Regards

FarmerJo

 

my_pwm_ip_v1_0_S00_AXI.vhd

[artvvb]

counter should be declared as a signal and std_logic_vector. Signals are the standard type for "variables" inside of a VHDL module.

Likely you will need to define the PWM# signals as std_logic instead of bit, VHDL has very strict typing, and things just work more smoothly if you can make the types of signals on the left and right side of an assignment match.

I don't believe that the constant keyword is required for PWM_COUNTER_MAX, generics are already evaluated when the design is synthesized, rather than when it is run.

I formatted my previous response in the way I did for a reason, one of the best ways to quickly get something to work is to learn from others, in this case, I'd recommend reading the template code that surrounds your code, if you can read and understand what is going on in that, you will find yourself well prepared to write your own.

[jpeyron]

Hi @FarmerJo,

I got the VHDL code to work. I attached both files for the custom IP. Also in the sdk code change the for loop to: for(i=0;i<35000; i++); for more visible results. So in the comparator statements that drive the PWM signal you need to compare similar types so I converted counter from and integer to a std_logic_vector. I have also attached my completed project in Vivado 2017.2.

cheers,

Jon

myip_v1_0.vhd

myip_v1_0_S00_AXI.vhd

pwm_controller.zip