A new interface specification for FPGA boards

[zygot]

While some FPGA board vendors have chosen to ignore the needs of their customers there is at least one trying to provide an interface specification with usable high performance IO. Check out http://syzygyfpga.io.  While I don't recommend or endorse the any FPGA board interface standard I have had good experiences with the products from this vendor; and they have offerings with Xilinx and Altera FPGA devices. For anyone wanting to use an FPGA with high performance A/D, D/A etc. this looks promising. My only question is what took so long?

 

[zygot]

The Brain-1 has started shipping from Crowd Supply. Check it out. This is not a solution for everything or everyone but it does have well thought out interfaces and open source tools. I will report on my first project with it.

[zygot]

It's been a while since I mentioned this and decided to offer an update, of sorts.

I bought all of the stuff offered though the Crowd Supply campaign. I did create a few projects to build a bitstream for the DAC and ADC PODs. The Brain-1 is a ZYNQ based board and has an interesting approach to the software design. I was not able to get the same results as the documentation for using the PODs inferred and it's clear that there are bugs to be resolved. The whole project has been absorbed into the normal Opal Kelly support systems. As of a few days ago there are no customer forum threads related to the SYSYGY project ( I could swear that I started one a few months back... ). The GIT sources show no signs of continued support. Opal Kelly has released a new Artix ( not ZYNQ ) main board with SYZYGY ports which is a welcome sign.

The work on the SYZYGY IO port designs yielded great success. I expect that they could attract IC vendors to use the platform instead of the expensive and clunky one's you typically see from non-FPGA vendors. Of course the key to making good IO interfaces is in FPGA pin assignments so anyone trying to conform to them can still make a mess of things. It grieves me that even after being told how to do IO right my preferred FPGA board vendor would rather stare into its upper colon. I heartily recommend all readers of this post to read the SYZYGY port specification. I'm not terribly fond of the micro-controller based DNA architecture but that's a design decision. I hope to get around to making a usable demo of at least a few PODs soon. ( I've had a few start/stop iterations already ). Not all of the PODs have any design support as of today.

I should point out a few things about Opal Kelly's business model that might be of interest to anyone interested. I have used their products in the past with success.

• Their main boards don't have a JTAG interface. This means that configuration and interaction between the board and a PC is done through a proprietary HDL and software interface. No support for Vivado or ISE debug IP. No options for other JTAG based services. All designs have the interface logic in it. The pride of the conpany seems to be in their Software support which is pretty nice and easy to use with a variety of PC applications and languages. I prefer the JTAG route but that's me.
• Opal Kelly's price point is higher than Digilent's in terms of FPGA device and on-board peripheral connectivity.
• Their main boards are small with high density connectors that can be attached to break out boards for prototyping. I you need a lot of IO this might just sell you a board.
• Now that they have a ARM-less ( different interface ) main board with SYZYGY IO ports there's a new vendor to support the projects that Digilent couldn't care less about.

I love free enterprise!