Retargeting Xilinx ISE Design Suite 13.2 based on a Nexys3 board to a Zybo or Spartan 6

[fank]

Dear digilent,

I am interested to retarget the following design to a zybo or spartan 6 FPGA. The design link is: https://reference.digilentinc.com/reference/pmod/pmodsf/start

( Nexys 3 VHDL Example - ISE 13.4 ). Could you please advise me how to do it? Thank you. F

[jpeyron]

Hi @Frank,

You add the .vhd files in a project. I believe i attached all of them bellow. Then use the .ucf  as a reference the either a different .ucf (ise)or .xdc (vivado) file of the board you are using. 

cheers,

Jon. 

clkdiv.vhd

EPP.vhd

EppPmod.vhd

PModSF.vhd

Nexys3_Master.ucf

[fank]

Hi @jpeyron,

The EPP module of that design has many I/O ports which are connected to some pins of the Nexys3.

My question is the following : Where should I tie all those pins in the zybo or spartan6lx9 ?

Thanks!

## onBoard USB controller
Net "EppAstb" LOC = H1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA
Net "EppDstb" LOC = K4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB
Net "EppWait" LOC = C2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD
Net "EppDB<0>" LOC = E1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0
Net "EppDB<1>" LOC = F4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1
Net "EppDB<2>" LOC = F3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2
Net "EppDB<3>" LOC = D2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3
Net "EppDB<4>" LOC = D1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4
Net "EppDB<5>" LOC = H7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5
Net "EppDB<6>" LOC = G6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6
Net "EppDB<7>" LOC = E4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7
Net "UsbFlag" LOC = F5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC

Regards,

F

 

[fank]

N.B: I have also a basys3 with me, in case it might be more suitable with that one.

F

[jpeyron]

Hi @Frank,

I am sorry I missed the usb controller portion of this project. The Zybo has a zynq processor that is directly connected to the usb. You would not be able to access the usb controller like in the Nexys 3 project. You could use the add a block function added to Vivado 2016.x and up. You would right click on the block design and select add a block. You would only add the PmodSF.vhd. This would be connected to a gpio ip block that would be connected to the zynq processor. I have attached a similar project that was done for the PmodAD1 with microblaze from one of our forum members. You could do the same process i described for the basys 3 but instead use microblaze. After looking at the Basys 3 schematics the usb controller is not accessible. I also looked at avnets spartan6 lx9 which the usb controller is not accessible. So you would not be able to use the full Nexys 3 project. Our atlys board here has the usb controller accessible and would be able to run the project with adding the correct ucf file.

cheers,

Jon

GPIO_add_a_block_(2).zip

[fank]

Hi @jpeyron,

Thank you for your answer. In a first step I will go for the zybo approach, but later I would like to read and write to the Pmodsf from the Microblaze.

1-     Do you think it could make sense to build a FSM in Verilog/VHDL, in order to drive EPP/PmodSF ports? Then, I could store the results of a read/write operation in a register accessible to the Microblaze.

2-     Or would it be much simpler to use a Xilinx IP (axi_SPI) to directly drive the I/O ports of the PmodSF? If yes, where can I get the driver code of that PmodSF for the microblaze (C code).

Once again thanks!

Regards,

F

[fank]

Hi @Jpeyron,

I went ahead and I followed your recommendations regarding the zybo approach.

I added the PmodSF.vhd as a block in Vivado and I made the following I/O ports as externals:

1-	P1 (out)  SEL 
2-	P2 (out)  SDI
3-	P3 (in)   SDO
4-	P4 (out)  SCK

Now my questions are the following:

1) How should I interface the following ports of the PmodSF with the axi_gpio?

      Address: in  std_logic_vector(7 downto 0);
      DataIn: in  std_logic_vector(7 downto 0);
      DataOut: out std_logic_vector(7 downto 0);
      Read: in  std_logic;
      Write: in  std_logic;
      DataRdy: out std_logic;

2) Which gpio functions do I need to read/write/erase and program the PmodSF from the Zynq Processor?

 

Thanks!

Regards,

F

 

 

[jpeyron]

Hi @fank,

The GPIO_add_a_block project i attached above is a complete project. which includes sdk code for interacting with the PmodAD1. There are a couple of differences in the spi connection but other than that it should be a good example of how you should be making your project. The GPIO_add_a_block takes vhdl code for the PmodAD1 and does a very similar process to what I had suggested to you. I have attached screen shots of the block design of the GPIO_add_a_block as well as the settings for the gpio block. I have also included the vhdl code and xdc used in the add a block along with the sdk code.

cheers,

Jon

 

main.c

pmodad1_hdl.txt

ZYBO_Master.xdc

[fank]

Hi @Jpeyron,

Maybe I did not express myself well. It is clear how the pmodad1 is interfaced with the GPIO. I verified the above design with a PmodAD1. But what is not clear is how I am going to connect the following I/O ports:

(Or should I interface those ports with the GPIO and control them with the help of the processor? I mean a similar connection between the led (15: 0) of the pmodad1 block and the input port gpio_io_i (15: 0) of the GPIO module. If yes, then this will answer my question.)

      Address: in  std_logic_vector(7 downto 0);
      DataIn: in  std_logic_vector(7 downto 0);
      DataOut: out std_logic_vector(7 downto 0);
      Read: in  std_logic;
      Write: in  std_logic;
      DataRdy: out std_logic;

In the Nexys 3 those ports were driven by the Epp module.

Thanks!

F

[jpeyron]

Hi @fank,

After talking with a co-worker more about your questions we decided that the best course of action would be to not use the add_a_block feature but instead use the PmodSF3 IP core(validated) that is here and change it to work for the PmodSF. You will want to look at the datasheet for the IC on the PmodSF3 here and compare it with the datasheet for the IC on the PmodSF here. Main change is that only single pin spi is available, so you can ignore all of the write dual and quad stuff. The 5 important commands have the same codes. So virtually no change necessary, other than cutting interrupt requirement and removing the quad/dual read/write tests. Sorry for the inconvenience. 

cheers,

Jon

[fank]

@jpeyron

Thanks!

Regards,

F