Anvyl Ethernet

[Andy Bradley]

Is there a doc on the connections from the Anvyl ethernet signals to the xps_ethernetlite IP core from Xilinx?  The core generates a few more pins than the Anvyl schematic has.
Thanks very much!

[jpeyron]

HI @Andy Bradley,

I am not at a computer where I can open the LwIP project and see which version of the LwIP was used. Here is the LightWeight IP Application Examples V3.2. If it is a different version. I would suggest to search for the correct version of the LightWeight IP Application Examples provided by Xilinx.  Documentation I have found besides the LwIP Application Examples is the schematic here and the Anvyl_demo_doc.pdf that is with the project demos off of the resource page here which also has the reference manual as well.

cheers,

Jon

 

[D@n]

You can also find an open source RMII ethernet controller here, as part of the OpenArty project, together with the software necessary to "ping" using that controller here.

I think there are other controllers available for the Anvyl on OpenCores, I just don't have any experience with them.

Dan

[Andy Bradley]

Hey thanks Dan. I'll check that out.
Andy

[Andy Bradley]

Thanks Jon.  I guess I didn't mention ther ver since my ise 14.7 only has 4.00 available.  I have the anvyl lwip demo but it doesn't include any vhdl files.  Its already mostly built.  The core i'm using, in schematic form, has the following connections:
phy tx clk pin not on anvyl
phy rx clk pin not on anvyl
phy dv pin
phy col pin not on anvyl
phy rx er pin
phy rst n pin
phy tx en pin
phy mdc pin
phy mdio pin
phy rx data pin(3:0) obviously i can just use d0/d1 but im not sure why.  More reading maybe?
phy tx data pin(3:0)

most of which match up but the anvyl board has:

eth txd1
eth txd0
eth txen
eth rxd1
eth rxd0
eth rxerr
eth crsdv
eth mdio
eth mdc
eth rst

And, the link to the xps ethernetlite ip core data sheet on the xilinx website is broken, so i bugged you guys.  They just sent me another data sheet so I'll have to check that out next.  Thanks very much,
Andy (newbie but commin' fast / i really dig this fpga stuff and i've put in a bunch of all nighters in the last few months)
I'm also part of a fairly experienced business outfit.

[D@n]

@Andy Bradley,

Hmm ... yeah, I see your problem.  With only two data bits connecting to a controller that needs or provides four looks like connecting a square peg into a round hole.

Have you found the data sheet for the ethernet part on the Anvyl?  From the data sheet it looks like the four wires are multiplex onto the two-wire outputs two at a time.  The standard I worked with on the Arty required four bits at a time using a 25MHz clock.  This appears to be two bits at a time on a 50MHz clock.

Dan

P.S.  I've never had nor used an Anvyl