create sine wave on dac using vhdl

[guneryunus]

i want to generate sine wave on dac (pmodda3)(http://www.analog.com/media/en/technical-documentation/data-sheets/AD5541A.pdf)and i am using spartan3e  but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please 

 

 

----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
 use ieee.numeric_std.all;

entity kecelikalem is
port(     clk: in  STD_LOGIC;
        reset  : in  STD_LOGIC;
        din:out std_logic;
          ldac:out std_logic:='1';
          cs :out std_logic:='1';
         sclk :out std_logic:='1');

end kecelikalem;

architecture Behavioral of kecelikalem is
  
signal a:integer range 0 to 3:=0;
signal i : integer range 0 to 18:=0;
type veri is array (2 downto 0) of std_logic_vector(15 downto 0);
signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000");
--signal sine :std_logic_vector(15 downto 0):="1100000000000011";
signal data :std_logic_vector(15 downto 0);
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 124999 := 0;
  begin
    frequency_divider: process (reset, clk) begin
        if (reset = '1') then
            temporal <= '0';
            counter <= 0;
        elsif rising_edge(clk) then
            if (counter = 124999) then
                temporal <= NOT(temporal);
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
  end process;
  sclk <= temporal;
process (temporal)

begin 
if falling_edge(temporal) then 
if(a=3) then
a<=0;
else 
data<=sine(a); 
if (i=18) then 
 a<=a+1;
 ldac<='1';
i<=0;
else
if (i=17) then 
    ldac <='0';
else
if (i=16) then 
   cs<='1';
    ldac <='1'; 
else
    cs<='0';
   din<=data(i); 
--din<=sine(i);
   ldac <='1';
end if ;
end if;
end if ;
i<=i+1;
end if;
end if;
end process;
end Behavioral;

 

[D@n]

@guneryunus,

In the editor when you post or reply there's a button that looks like <>

Please use that button, and then paste your code in the section it creates, so that your indentation doesn't get lost.

As it is, I'm struggling to read your code.

The warning really means what it says: certain of your data lines are *never* changing.  If that's what you want, then ignore the warning.  Otherwise you may need to do something to fix whatever is wrong with your code.

Dan

[artvvb]

@guneryunus

Lets take these in order.

Signal <sine> is used but never assigned... This is fairly straightforward. You never have the sine signal on the left hand side of an assign statement, vivado couldn't figure out what you wanted to make it, so it is tying to a default constant. I am unsure where this signal is supposed to be coming from as well, you will have to explain more.

Latch <data_N> has a constant value of zero... This is inherited from the <sine> warning, since you are setting data equal to a subset of sine, but never setting sine.

CLK Net:temporal... This is a logic gated clock problem, I wrote up an answer to another thread this morning in regards to the same problem, you may wish to review that thread.

Thanks,

Arthur

[guneryunus]

7 minutes ago, D@n said:

@guneryunus,

In the editor when you post or reply there's a button that looks like <>

Please use that button, and then paste your code in the section it creates, so that your indentation doesn't get lost.

As it is, I'm struggling to read your code.

The warning really means what it says: certain of your data lines are *never* changing.  If that's what you want, then ignore the warning.  Otherwise you may need to do something to fix whatever is wrong with your code.

Dan

thank i will use <> .I want to put all the values in order. I need to do this bit by bit.dac works in series

[artvvb]

Is the sine signal intended to be constant? That is what all of the warnings except the last are trying to tell you. On a second read through, it looks like you are trying to iterate through a constant array and send the bits stored in it out to the dac.

The important part about using <> is that it maintains formatting a little better. Please try to make sure that your code is indented so that other people can read it, even when using the code block (<>).

[hamster]

HI,

This is a case when using shift registers can make your life so much easier in the constants - you can almost draw what you want to see

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dac is
    Port ( clk      : in STD_LOGIC;
           dac_clk  : out STD_LOGIC;
           dac_cs   : out STD_LOGIC;
           dac_ld   : out STD_LOGIC;
           dac_data : out STD_LOGIC);
end dac;

architecture Behavioral of dac is
    signal clk_sr   : std_logic_vector(3 downto 0)  := "0011";
    signal cs_sr    : std_logic_vector(19 downto 0) := x"C0003";
    signal data_sr  : std_logic_vector(19 downto 0) := x"00000";
    signal ld_sr    : std_logic_vector(19 downto 0) := x"FFFFE";
    signal counter  : unsigned(2 downto 0) := "000";
    
    type t_table is array(0 to 7) of std_logic_vector(15 downto 0);
    signal table : t_table := ( x"8000",x"E000",x"FFFF",x"E000",
                                x"8000",x"2000",x"0000",x"2000");
         
begin

process(clk)
    begin
        if rising_edge(clk) then
            -- Set the outputs 
            dac_clk  <= clk_sr(clk_sr'high);
            dac_cs   <= cs_sr(cs_sr'high);
            dac_data <= data_sr(data_sr'high);
            dac_ld   <= ld_sr(ld_sr'high);
            
            -- shift the data shift registers
            if clk_sr = "1001" then 
                cs_sr   <= cs_sr(cs_sr'high-1 downto 0)     & cs_sr(cs_sr'high);            
                data_sr <= data_sr(data_sr'high-1 downto 0) & data_sr(data_sr'high);
                ld_sr   <= ld_sr(ld_sr'high-1 downto 0)     & ld_sr(ld_sr'high);
                
                -- put a new data value in the data shift register, when needed needed
                if cs_sr(15) = '1' and cs_sr(14) = '0' then
                    data_sr(15 downto 0) <= table(to_integer(counter));
                    counter <= counter + 1;
                end if;
            end if;
            -- Shift the clock shift registers
            clk_sr   <= clk_sr(clk_sr'high-1 downto 0)     & clk_sr(clk_sr'high);            
            
        end if;
    end process;

end Behavioral;

I've attached the simulation image

[vt96mta]

Hello Hamster, if i want to generate bpsk, how to phase reserval? please help me.