generate sine wave on dac

[guneryunus]

i want to generate sine wave on dac (http://store.digilentinc.com/pmod-da3-one-16-bit-d-a-output/) i am using 16 bit dac and i am using spartan 3e . i cant do it . help me ??

 

 

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity pmod_da3 is
    Port ( clk        : in STD_LOGIC;
           CSn        : out STD_LOGIC;
           LDACn      : out STD_LOGIC;
           SCLK       : out STD_LOGIC;
           SDAT       : out STD_LOGIC;
           data_taken : out STD_LOGIC := '0';
           level      : in STD_LOGIC_VECTOR (15 downto 0));
end pmod_da3;

architecture Behavioral of pmod_da3 is
    type array_type is array (0 to 1 ) of std_logic_vector(15 downto 0);
     signal array_name :array_type:=("0000000000000001","0000000000000011");
    constant len           : integer := 19;
    signal CSn_shift_reg   : std_logic_vector(len-1 downto 0) := (len-17 downto 0 => '1', others => '0');
    signal LDACn_shift_reg : std_logic_vector(len-1 downto 0) := (1 => '0', others => '1');
    signal SDAT_shift_reg  : std_logic_vector(len-1 downto 0) := (others => '0');
    signal sclk_state      : std_logic_vector(1 downto 0)  := "00";
     
begin
    SCLK  <= sclk_state(0);
    LDACn <= LDACn_shift_reg(0);
    CSn   <= CSn_shift_reg(0);

clk_proc: process(clk)
 variable a: integer range 0 to 15;
  begin
 
        if rising_edge(clk) then
            data_taken <= '0';
            case sclk_state is 
                when "00" =>   sclk_state <= "01";
                                -- Mpve the shift regeister along
                               SDAT  <= array_name(a);
                                         a:=a+1;
                                         if (a=15) then 
                                         a:=0;
                                        end if;
                              -- SDAT_shift_reg  <= SDAT_shift_reg(len-2 downto 0)  & 'X';
                               LDACn_shift_reg <= LDACn_shift_reg(len-2 downto 0) & LDACn_shift_reg(len-1);
                               if LDACn_shift_reg(1) = '0' then
                                  SDAT_shift_reg(SDAT_shift_reg'high downto SDAT_shift_reg'high-level'high) <= level;
                                  data_taken <= '1';
                               end if;
                when "01" =>   sclk_state <= "10";
                when "10" =>   sclk_state <= "11";
                               CSn_shift_reg   <= CSn_shift_reg(len-2 downto 0)   & CSn_shift_reg(len-1);
                when others => sclk_state <= "00";
            end case;
        end if;
    end process;
end Behavioral;
 

[D@n]

@guneryunus,

A couple of questions:

1. What are you doing to test?  In other words, how do you know this doesn't work?
2. If you send constant values through the DAC, can you read changes that make sense when using a voltmeter?
3. Have you simulated this logic?  Can you provide a trace result of your simulation?
4. What speed is your clock running at?

Dan

[jpeyron]

HI @guneryunus,

Here is a forum thread that discusses and links to some tutorial/examples of a few different ways to create a sine wave.

cheers,

Jon

[guneryunus]

11 minutes ago, D@n said:

@guneryunus,

A couple of questions:

1. What are you doing to test?  In other words, how do you know this doesn't work?
2. If you send constant values through the DAC, can you read changes that make sense when using a voltmeter?
3. Have you simulated this logic?  Can you provide a trace result of your simulation?
4. What speed is your clock running at?

Dan

i am using ise 14.7 and the speed is 50 mhz. my dac is working in series

[D@n]

@guneryunus,

Hmm ... something about that doesn't look right (yet).

1. It's kind of hard to draw conclusions from your simulated waveform, since the traces aren't individually identified. 
2. It also looks like you captured that trace with a camera taking a snapshot of your screen, rather than a screen capture.  If you could do a screen capture, I think the result would come across clearer.
3. I'm not seeing a valid SCLK on your trace.
4. Is the multilevel waveform supposed to be a sine wave?  If so, it's transitioning *WAY* too fast.  It should transition once per D/A output, not once per clock.  Further, if it is such a trace, you've saturated your sinewave pretty badly.  The trace should *look* like a sinewave, rather than a clipped triangle wave.
5. With all that said, it is hard to be conclusive since I can't tell which trace lines connect to which wires in your simulation.
6. Can you create a simulation trace that looks like figure 3 on page 5 of the D/A data sheet?

Dan

[D@n]

@guneryunus,

Ok, I see the trace names now.  I was confused before by the level trace not showing anything.  Now that makes sense.

Still, SCLK doesn't look right.  Perhaps you could capture just the single SCLK bit instead of the SCLK state?

You've  also told me nothing about how you know that the DAC isn't working.  Can you tell me what test it is failing?

Thanks,

Dan

[guneryunus]

3 hours ago, D@n said:

@guneryunus,

Hmm ... something about that doesn't look right (yet).

1. It's kind of hard to draw conclusions from your simulated waveform, since the traces aren't individually identified. 
2. It also looks like you captured that trace with a camera taking a snapshot of your screen, rather than a screen capture.  If you could do a screen capture, I think the result would come across clearer.
3. I'm not seeing a valid SCLK on your trace.
4. Is the multilevel waveform supposed to be a sine wave?  If so, it's transitioning *WAY* too fast.  It should transition once per D/A output, not once per clock.  Further, if it is such a trace, you've saturated your sinewave pretty badly.  The trace should *look* like a sinewave, rather than a clipped triangle wave.
5. With all that said, it is hard to be conclusive since I can't tell which trace lines connect to which wires in your simulation.
6. Can you create a simulation trace that looks like figure 3 on page 5 of the D/A data sheet?

Dan

again i wrote codes you can see easly figure

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
 use ieee.numeric_std.all;

entity kecelikalem is
port( clk:in std_logic;
      din:out std_logic;
        ldac:out std_logic:='1';
        cs :out std_logic:='0';
        data_taken : out STD_LOGIC := '0';
        sclk :out std_logic:='1'
);

end kecelikalem;

architecture Behavioral of kecelikalem is

signal i : integer range 0 to 15;

--type veri is array (0) of std_logic_vector(15 downto 0);
signal sine :std_logic_vector(15 downto 0):="1100000000000001";
 signal sclk_state      : std_logic_vector(1 downto 0)  := "00";

begin
--SCLK  <= sclk_state(1);
    --ldac <= '0';
    --cs<='1';
     sclk<=clk;
process (clk)
begin 
if rising_edge(clk) then 
data_taken <= '0';
case sclk_state is 
when "00"=> sclk_state<="01";
-- register kaydırma 
ldac<='1';
cs<='0';
din<=sine(i);
i<=i+1;
--if (i=15) then 
--i<=0;
--end if ;

when "01"=> sclk_state<="10";
cs<='1';
when "10"=> sclk_state<="11";
ldac<='0';
when others => sclk_state<="00";

end case ;
end if;
end process;

end Behavioral;
 

[D@n]

@guneryunus,

Yeah, you're not matching the spec yet.  There should only be 16 rising edges of SLK when CS is low, no more.  Check the reference I showed you earlier.  Try to make your simulation match that reference.

Dan