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RajatRao

Creating an AXI forwarder IP

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Hello,

I am trying to create an IP that reorders AXI DRAM addresses, similar to the one described in Xilinx xapp792. The main purpose is to change from Row/Bank/Column to Bank/Row/Column addressing. A portion of the block design where the IP will be used is attached.

When I create this IP, it gets its own address space. However, it should only be a forwarder, like the axi interconnect. I know I should be setting some parameters in IP packager, but I don't know what those are. Can anyone help me out with this?

Thanks,

Rajat Rao

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Thanks for pointing me to those tutorials.

The tutorials explain how to create an IP with AXI4 interface. I am quite familiar with this. In this case, the IP created will have its own address space because it needs to be addressable.

However, the IP I am looking to create should behave similar to the AXI interconnect. It just forwards AXI transactions from one port to the other. This means that it should not have an address space of its own.

Specifically, I'm looking for what settings to change in IP packager that will allow me to do this.

The AXI interconnect port has Type 'hier'. Maybe this needs to be set somewhere, but I don't know where or how.

 

Thanks,

Rajat Rao

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@RajatRao,

Why don't you just reconfigure the memory to be in the different byte order?  That's all within the options that the memory interface generator uses.  Alternatively, you could make your own memory and just swap the wires--but the bank/row/column vs row/bank/column is within the configurability of the memory controller.

Dan

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Hi @D@n,

Yes the MIG IP does have the configurability. Unfortunately, I'm not using MIG - I'm using Zynq which has an in-built DDRC. I don't think the Zynq DDRC can be configured, can it?

Any ideas?

Thanks,

Rajat Rao

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