Memory Access

[shis]

I want to store a huge matrix of size 1024*968 in FPGA which is constant. Which can be done by storing in block ram or distributed ram. But for low cost FPGA's due non availabilty of huge memory it is not possible. Is there any other way as i only require to read that matrix one column at a time. Is that possible to  read that matrix from external memory.

[artvvb]

@shis

Yes, it is possible, but it can be more challenging to work with. Some of our low cost boards have DDR memory which can be accessed from the FPGA, if you can get the controller correct, or find one with interfaces that work for you. We also sell some peripherals that could work for you, the Pmod SF3 for example has a fairly involved programming and reading sequence that can be managed through the FPGA (though it's 32MB of memory may not be enough, depending on the bit depth of your matrix entries). You may also want to look into various ways of compressing your matrix, but this could depend on what your data looks like.

Hope this helps,

Arthur

[D@n]

@shis,

If you only need to read the matrix one column at a time, transpose it.  Memory works well when you attempt to read adjacent memory areas or in sequence.

Which memory you choose also depends upon your timing needs.  Most of the flash devices on the boards Digilent sells can read 8'bits every 20-40ns.  However, they may take up to 240ns to get that first byte through.  (Some of this depends on whether you are running the flash serial clock with a 50MHz or a 100MHz clock)  Open source wishbone controllers  are available, should you want one.

SDRAM can be much faster.  My Arty can read 128-bits every 12ns or so, although the first request may take about 300ns to complete--if I recall correctly, it's been some time since I measured that latency.  I'm now working with a Nexys Video that can read 128-bits every 10ns, but I have no idea what the latency is through the controller.  Should you choose to wish to use SDRAM, you'll probably want to initialize the SDRAM from the flash anyway.

If you'll notice, I just gave two numbers for the speeds of each of those parts.  The first is the speed you should be able to achieve if you read your values in sequence.  The second, if you read your values in random order (i.e. column order) from your device.

Just a thought or two,

Dan

[shis]

Thank you sir for your reply.....Currently i am having NEXYS 4 board which have DDR2 with 128 MB memory. I want my design to work atleast at 100Mhz clk...I have tried to access the DDR2 memory and for that i have created a MIG ip in XILINX ISE. But after so many trials i have failed..Transposing the matrix can't help as i want to read any particular column depending on a particular index..Encryption is possible as there are so many zeros in any column..But that is also not enough as Distributed memory automatically ignores zeros. I have also tried to reduce the bit-length . So requirement of memory reduced but that is also not enough to fit the design in the NEXYS 4 board.

Can you give me any idea about how to use DDR2 memory just as a rom. For my application 11 bit data is enough. but reading should be done at 100mhz.

If you can plz give an road map to interface the DDR 2 memory.

 

[jpeyron]

Hi @shis,

Here is a SRAM to DDR conponent link that was made because there is a problem mapping the MIG is ISE. In short, the tools do not see the MIG generated UCF file. Here is a basic vivado microblaze tutorial that uses the MIG IP block. Here is the resource page. Here is our github. In projects->user demo here is some vhdl code for the memory.

cheers,

Jon