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lucileklang

Locked IPs & Place_design ERROR in Vivado with Zybo DMA Audio Demo

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Hello,

I just received my Zybo board, and I would like to use the DMA Audio demo to have audio input and output ready-to-run on my board. I chose to put the project into Vivado to be able to see the block design and make changes in the design later on. I did the following steps :
- Downloaded the ZIP archive you can find on https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start
- Created the project with TCL command and create_design.tcl file
- Opened block design by adding the BD file as a design source in Vivado
- Added the d_axi_i2s_audio_v2_0 IP to Vivado

When I tried to synthesize, implement and generate the bitstream, I got an error saying :

[filemgmt 20-1366] Unable to reset target(s) for the following file is locked: C:/Users/Lucile/Zybo-DMA-3essai/Zybo-DMA/src/bd/design_1/design_1.bd
Locked reason: 
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
design_1_auto_pc_0
design_1_processing_system7_0_axi_periph_0
design_1_processing_system7_0_0
design_1_axi_mem_intercon_0
design_1_xlconstant_0_0
design_1_axi_iic_0_0
design_1_rst_processing_system7_0_100M_0
design_1_d_axi_i2s_audio_0_0
design_1_xbar_0
design_1_xbar_1
design_1_auto_us_0
design_1_auto_us_1
design_1_auto_pc_1


So I looked for some support and I followed https://www.xilinx.com/support/answers/63645.html, and in the design source the IPs look unlocked as said in the previous page, but I still get the same error. It also puts me this error :

[BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
[...same list...]

I tried deleting each block and putting it back in the design, but it didn't change anything. Does someone have a solution for this ? It keeps me from generating the bitstream and exporting it to SDK.

I also have several errors of placement, first I got this one :

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity: 
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  Out  RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 1 sites.
    Term: ac_bclk

I found out that the port ac_bclk was mapped to pin K18, but btns_4bits_tri_i[0] is also mapped to K18. Is it an error that others had with this demo ?
To solve this I mapped ac_bclk to pin K14 which was free.

I then got another error of the same type :

  • [Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: IIC_scl_o Term: IIC_scl_t Term: IIC_sda_o Term: and IIC_sda_t

    [Place 30-374] IO placer failed to find a solution
    Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

    +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    |                                                                     IO Placement : Bank Stats                                                                           |
    +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
    | Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
    +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
    |  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
    | 13 |     0 |     0 |                                                                        |                                          |        |        |        |     |
    | 34 |    50 |     6 | LVCMOS33(6)                                                            |                                          |        |  +3.30 |    YES |     |
    | 35 |    50 |     7 | LVCMOS33(7)                                                            |                                          |        |  +3.30 |    YES |     |
    +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
    |    |   100 |    13 |                                                                        |                                          |        |        |        |     |
    +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

    IO Placement:
    +--------+----------------------+-----------------+----------------------+----------------------+----------------------+
    | BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
    +--------+----------------------+-----------------+----------------------+----------------------+----------------------+
    | 34     | IIC_scl_i            | LVCMOS33        | IOB_X0Y24            | N18                  |                      |
    |        | IIC_sda_i            | LVCMOS33        | IOB_X0Y4             | N17                  |                      |
    |        | ac_mclk              | LVCMOS33        | IOB_X0Y0             | T19                  |                      |
    |        | ac_muten[0]          | LVCMOS33        | IOB_X0Y3             | P18                  |                      |
    |        | btns_4bits_tri_i[1]  | LVCMOS33        | IOB_X0Y1             | P16                  |                      |
    |        | btns_4bits_tri_i[3]  | LVCMOS33        | IOB_X0Y36            | Y16                  |                      |
    +--------+----------------------+-----------------+----------------------+----------------------+----------------------+
    | 35     | ac_bclk              | LVCMOS33        | IOB_X0Y60            | K14                  |                      |
    |        | ac_pbdat             | LVCMOS33        | IOB_X0Y84            | M17                  |                      |
    |        | ac_pblrc             | LVCMOS33        | IOB_X0Y77            | L17                  |                      |
    |        | ac_recdat            | LVCMOS33        | IOB_X0Y76            | K17                  |                      |
    |        | ac_reclrc            | LVCMOS33        | IOB_X0Y83            | M18                  |                      |
    |        | btns_4bits_tri_i[0]  | LVCMOS33        | IOB_X0Y75            | K18                  |                      |
    |        | btns_4bits_tri_i[2]  | LVCMOS33        | IOB_X0Y80            | K19                  |                      |
    +--------+----------------------+-----------------+----------------------+----------------------+----------------------+

We can see that ac_bclk has been mapped to K14 which is what I wanted but why do I still get the previous error about ac_bclk ? 
And also where should  I map those 4 new ports ? Is it normal to have that many errors on a demo which should work without any modification ?

Any help would be greatly appreciated ! :)
Regards,
Lucile

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@lucileklang

Which version of Vivado are you using?

This error is typically seen when using a version more recent than the demo was developed for or updated to. The DMA Audio demo was built for Vivado 2016.4.

If you are in a 2017 version of Vivado, try upgrading the IPs by clicking Tools / Report / Report IP Status in the top menu bar. From there select Upgrade Selected in the IP report sub-window that pops up at the bottom of the screen.

Once you have the bitstream generated, launched SDK, and imported the SDK projects, you will likely need to Regenerate BSP Sources by right clicking on the *_bsp project and selecting that option.

If Xilinx didn't update their IP or drivers beyond recognition (which is somewhat rare) this should get the project up and running.

Hope this helps,

Arthur

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Hi,

I started again from the beginning and updated the IPs as you said. The Output products were then generated. When I try to generate the bitstream, I still got many errors :
 

[BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
design_1_axi_dma_0_0
design_1_auto_pc_0
design_1_processing_system7_0_axi_periph_0
design_1_processing_system7_0_0
design_1_axi_mem_intercon_0
design_1_axi_gpio_0_0
design_1_xlconcat_0_0
design_1_xlconstant_0_0
design_1_axi_iic_0_0
design_1_rst_processing_system7_0_100M_0
design_1_d_axi_i2s_audio_0_0
design_1_xbar_0
design_1_xbar_1
design_1_auto_us_0
design_1_auto_us_1
design_1_auto_pc_1

Plus the ones I already had before that were due to a wrong mapping of ac_bclk (to K18 as though this pin is used for something else) and to a spelling mistake in the constraints :
set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports iic_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports iic_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA

I think it should be :
set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports IIC_scl_i]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports IIC_sda_i]; #IO_L23P_T3_34 Sch=AC_SDA

as I get the warnings at the corresponding lines :
 [Common 17-55] 'set_property' expects at least one object. ["C:/Users/Lucile/Zybo-DMA-4essai/Zybo-DMA/src/constraints/ZYBO_Master.xdc":44]
[Common 17-55] 'set_property' expects at least one object. ["C:/Users/Lucile/Zybo-DMA-4essai/Zybo-DMA/src/constraints/ZYBO_Master.xdc":45]

Can you confirm this ?

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@artvvb I am using Vivado 2017.2.
Thanks @jpeyron, I saw it yesterday, but yesterday I didn't work because when opening the design_1_bd.tcl file AFTER creating the project, the version was updated to 2017.2 but the changes weren't (I guess) taken in account everywhere. Today I tried it again by changing the version BEFORE creating the project, and was able to generate the bitstream.

Thank you both for your help !
Lucile

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Posted (edited)
18 hours ago, artvvb said:

 

Once you have the bitstream generated, launched SDK, and imported the SDK projects, you will likely need to Regenerate BSP Sources by right clicking on the *_bsp project and selecting that option.

If Xilinx didn't update their IP or drivers beyond recognition (which is somewhat rare) this should get the project up and running.

Hi @artvvb,
I now launched the project in SDK as said in the tutorial, but it fails to generate the BSP sources, even if I click on "regenerate bsp sources" as you told me. Here's the error I get :
 

10:02:56 INFO    : Launching XSCT server: xsct.bat -interactive C:\Users\Lucile\Zybo-DMA-5essai\Zybo-DMA\proj\DMA.sdk\temp_xsdb_launch_script.tcl
10:02:56 INFO    : XSCT server has started successfully.
10:02:56 INFO    : Successfully done setting XSCT server connection channel  
10:02:56 INFO    : Successfully done setting SDK workspace  
10:02:56 INFO    : Registering command handlers for SDK TCF services
10:03:02 INFO    : Processing command line option -hwspec C:/Users/Lucile/Zybo-DMA-5essai/Zybo-DMA/proj/DMA.sdk/design_1_wrapper.hdf.
10:03:02 INFO    : Checking for hwspec changes in the project design_1_wrapper_hw_platform_0.

10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core gpio of version 4.1 not found in repositories

10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core iic of version 3.2 not found in repositories
ERROR: [Hsi 55-1452] Error: running open_sw_design.

10:03:02 ERROR    :  [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.
10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core gpio of version 4.1 not found in repositories

10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core iic of version 3.2 not found in repositories

10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1452] Error: running open_sw_design.

10:03:02 INFO    : Unable to read in MSS file C:\Users\Lucile\Zybo-DMA-5essai\Zybo-DMA\proj\DMA.sdk\dma_bsp\system.mss : null
10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core gpio of version 4.1 not found in repositories

10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core iic of version 3.2 not found in repositories

10:03:02 ERROR    : (XSDB Server)ERROR: [Hsi 55-1452] Error: running open_sw_design.

10:03:02 ERROR    : Failed in generating sources
10:03:02 INFO    : BSP Project P/dma_bsp has been successfully migrated.

 

And then when I regenerate the sources :
 

10:04:21 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core gpio of version 4.1 not found in repositories
ERROR: [Hsi 55-1594] Core iic of version 3.2 not found in repositories

10:04:21 ERROR    : (XSDB Server)ERROR: [Hsi 55-1452] Error: running open_sw_design.

10:04:21 ERROR    :  [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors.
10:04:21 ERROR    : (XSDB Server)ERROR: [Hsi 55-1594] Core gpio of version 4.1 not found in repositories
ERROR: [Hsi 55-1594] Core iic of version 3.2 not found in repositories

10:04:21 ERROR    : (XSDB Server)ERROR: [Hsi 55-1452] Error: running open_sw_design.

10:04:21 INFO    : Unable to read in MSS file C:\Users\Lucile\Zybo-DMA-5essai\Zybo-DMA\proj\DMA.sdk\dma_bsp\system.mss : null
10:04:21 ERROR    : Unexpected error occurred during generating bsp sources
java.lang.reflect.InvocationTargetException
    at org.eclipse.jface.operation.ModalContext.run(ModalContext.java:398)
    at org.eclipse.jface.dialogs.ProgressMonitorDialog.run(ProgressMonitorDialog.java:481)
    at org.eclipse.ui.internal.progress.ProgressMonitorJobsDialog.run(ProgressMonitorJobsDialog.java:242)
    at org.eclipse.ui.internal.progress.ProgressManager$3.run(ProgressManager.java:895)
    at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
    at org.eclipse.ui.internal.progress.ProgressManager.busyCursorWhile(ProgressManager.java:930)
    at org.eclipse.ui.internal.progress.ProgressManager.busyCursorWhile(ProgressManager.java:905)
    at org.eclipse.ui.internal.progress.ProgressManager.run(ProgressManager.java:1078)
    at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.execute(RegenBspSourcesHandler.java:124)

 

Looks like the core IPs are not found in the repositories. Actually in the dma_bsp no ps7_cortexa9_0 has been generated at all, is that normal ?
I copied this repository from another SDK project and pasted it in my dma_bsp. I downloaded the gpio and iic drivers in Github https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers and put them in ps7_cortexa9_0/libsrc. I checked the versions : gpio is version 4.1 as wanted by SDK and iic is version 3.0 instead of 3.2 so I changed in the system.mss file the expected iic version to 3.0. I finally names the repository drivers gpio_v4_1 and iic_v3_0 to match the other driver's notation.
Unfortunately that doesn't seem to do anything. Can anybody help ?
Thanks

Edited by lucileklang
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Solved the problem by creating a new Hardware Platform Specifiation (with the design_1_wrapper.hdf file), a new BSP based on this platform and a new application where I copied the c files. 
Thanks for your help !

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Hi,

I also solved the problem of the mapping  of the signal ac_bclk, which was mapped to pin K18, the same pin as the signal btns_4bits_i[0]. I didn't change the mapping of ac_blck because on the schematics (https://reference.digilentinc.com/_media/reference/programmable-logic/zybo/zybo_sch.pdf) the K18 pin is dedicated to this clock. But I saw also on the schematics that btns_4bits_i[1] and btns_4bits_i[3] were mapped to the pins names BTN1 and BTN3, but btns_4bits_i[0] and btns_4bits_i[2] were not. I assumed that this was an error and mapped those signals to BTN0 and BTN2 respectively. The implementation and the generation of the bitstream now complete, and everything works fine with the software part.

Regards,

Lucile

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