I just received my Zybo board, and I would like to use the DMA Audio demo to have audio input and output ready-to-run on my board. I chose to put the project into Vivado to be able to see the block design and make changes in the design later on. I did the following steps :
- Downloaded the ZIP archive you can find on https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start
- Created the project with TCL command and create_design.tcl file
- Opened block design by adding the BD file as a design source in Vivado
- Added the d_axi_i2s_audio_v2_0 IP to Vivado
When I tried to synthesize, implement and generate the bitstream, I got an error saying :
[filemgmt 20-1366] Unable to reset target(s) for the following file is locked: C:/Users/Lucile/Zybo-DMA-3essai/Zybo-DMA/src/bd/design_1/design_1.bd
Locked reason:
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
design_1_auto_pc_0
design_1_processing_system7_0_axi_periph_0
design_1_processing_system7_0_0
design_1_axi_mem_intercon_0
design_1_xlconstant_0_0
design_1_axi_iic_0_0
design_1_rst_processing_system7_0_100M_0
design_1_d_axi_i2s_audio_0_0
design_1_xbar_0
design_1_xbar_1
design_1_auto_us_0
design_1_auto_us_1
design_1_auto_pc_1
So I looked for some support and I followed https://www.xilinx.com/support/answers/63645.html, and in the design source the IPs look unlocked as said in the previous page, but I still get the same error. It also puts me this error :
[BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
[...same list...]
I tried deleting each block and putting it back in the design, but it didn't change anything. Does someone have a solution for this ? It keeps me from generating the bitstream and exporting it to SDK.
I also have several errors of placement, first I got this one :
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 1 sites.
Term: ac_bclk
I found out that the port ac_bclk was mapped to pin K18, but btns_4bits_tri_i[0] is also mapped to K18. Is it an error that others had with this demo ?
To solve this I mapped ac_bclk to pin K14 which was free.
I then got another error of the same type :
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: IIC_scl_o Term: IIC_scl_t Term: IIC_sda_o Term: and IIC_sda_t
[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.
We can see that ac_bclk has been mapped to K14 which is what I wanted but why do I still get the previous error about ac_bclk ?
And also where should I map those 4 new ports ? Is it normal to have that many errors on a demo which should work without any modification ?
Any help would be greatly appreciated !
Regards,
Lucile
Question
lucileklang
Hello,
I just received my Zybo board, and I would like to use the DMA Audio demo to have audio input and output ready-to-run on my board. I chose to put the project into Vivado to be able to see the block design and make changes in the design later on. I did the following steps :
- Downloaded the ZIP archive you can find on https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-dma-audio-demo/start
- Created the project with TCL command and create_design.tcl file
- Opened block design by adding the BD file as a design source in Vivado
- Added the d_axi_i2s_audio_v2_0 IP to Vivado
When I tried to synthesize, implement and generate the bitstream, I got an error saying :
[filemgmt 20-1366] Unable to reset target(s) for the following file is locked: C:/Users/Lucile/Zybo-DMA-3essai/Zybo-DMA/src/bd/design_1/design_1.bd
Locked reason:
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
design_1_auto_pc_0
design_1_processing_system7_0_axi_periph_0
design_1_processing_system7_0_0
design_1_axi_mem_intercon_0
design_1_xlconstant_0_0
design_1_axi_iic_0_0
design_1_rst_processing_system7_0_100M_0
design_1_d_axi_i2s_audio_0_0
design_1_xbar_0
design_1_xbar_1
design_1_auto_us_0
design_1_auto_us_1
design_1_auto_pc_1
So I looked for some support and I followed https://www.xilinx.com/support/answers/63645.html, and in the design source the IPs look unlocked as said in the previous page, but I still get the same error. It also puts me this error :
[BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
[...same list...]
I tried deleting each block and putting it back in the design, but it didn't change anything. Does someone have a solution for this ? It keeps me from generating the bitstream and exporting it to SDK.
I also have several errors of placement, first I got this one :
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 1 sites.
Term: ac_bclk
I found out that the port ac_bclk was mapped to pin K18, but btns_4bits_tri_i[0] is also mapped to K18. Is it an error that others had with this demo ?
To solve this I mapped ac_bclk to pin K14 which was free.
I then got another error of the same type :
[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 13 | 0 | 0 | | | | | | |
| 34 | 50 | 6 | LVCMOS33(6) | | | +3.30 | YES | |
| 35 | 50 | 7 | LVCMOS33(7) | | | +3.30 | YES | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 100 | 13 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34 | IIC_scl_i | LVCMOS33 | IOB_X0Y24 | N18 | |
| | IIC_sda_i | LVCMOS33 | IOB_X0Y4 | N17 | |
| | ac_mclk | LVCMOS33 | IOB_X0Y0 | T19 | |
| | ac_muten[0] | LVCMOS33 | IOB_X0Y3 | P18 | |
| | btns_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y1 | P16 | |
| | btns_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y36 | Y16 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35 | ac_bclk | LVCMOS33 | IOB_X0Y60 | K14 | |
| | ac_pbdat | LVCMOS33 | IOB_X0Y84 | M17 | |
| | ac_pblrc | LVCMOS33 | IOB_X0Y77 | L17 | |
| | ac_recdat | LVCMOS33 | IOB_X0Y76 | K17 | |
| | ac_reclrc | LVCMOS33 | IOB_X0Y83 | M18 | |
| | btns_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y75 | K18 | |
| | btns_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y80 | K19 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
And also where should I map those 4 new ports ? Is it normal to have that many errors on a demo which should work without any modification ?
Any help would be greatly appreciated !
Regards,
Lucile
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