Vivado SDK Hello World Outputs Nothing to Terminal

[electronicsdevices]

I'm using Vivado 2017 and a ZYBO board, and I have had success generating bitstreams and using the SDK to print output to the terminal (be it PuTTY or the SDK terminal). However, there are other times where the bitstream has been successfully generated and a simple hello world will print nothing to the terminal. Why is this?

[jpeyron]

Hi @electronicsdevices,

I have not see any issues on the Xilinx forums or the Digilents forums dealing with the hello world on zynq using Vivado 2017. Which version of Vivado are you using 2017.1 or 2017.2? Are you using the board files for the zybo or are you choosing the fpga part and setting up the Zynq processor manually? Using the board files, I just ran through the hello world for both Vivado 2017.1 and 2017.2 for the zybo with out issue. I have not experienced this issue. In general most of the time I have issues with the hello world for any board I have forgotten to either change the baud rate to 115200 on zynq boards or did not choose the correct com port on the serial terminal. Could you attach a screen shot of the terminal settings and the sdk log/problems the next time you experience this issue. When running the application in SDK are you choosing run as-> 1 Launch on Hardware (System Debugger)?  

cheers,

Jon

[electronicsdevices]

@jpeyron

I'm using 2017.1 and I installed the board files a while ago for the ZYBO board.

I can do you one better and give you a copy of my current project:

https://github.com/electricbluefire/MMult/blob/master/7-25-17_VHDL_2x2_MMult.zip

 

 

[jpeyron]

Hi @electronicsdevices,

I reached out to a co-worker that has been doing some design work in Vivado 2017.1. They said that Vivado 2017.1 has had some bugs with updating hardware changes. It will show in synthesis that it is still using an out of date block design but will not stop the generate bitstream process. You need to manually stop generating the bitstream and update the top file. I have been having issues with you IP being locked even after I change the IP repo to look at \7-25-17_VHDL_2x2_MMult\7-25-17_VHDL_2x2_MMult.srcs\sources_1\bd\design_1\ip\design_1_myip2x2VHDL_0_0 in the project you linked to. Also why are you using both uart 0 and uart 1. I have had issues with the basis hello world when not using just uart 1. I have included screen shots of both of our configuration of the zynq processor below. If you are not needing both uarts then I would suggest to remove uart 0 from the zynq processor and try the hello world again.

cheers,

Jon

[electronicsdevices]

@jpeyron

Thank you. Yeah that's really strange. When I switched to just UART1, I can receive terminal output from the SDK terminal.

I do have a follow-up question: How do I input matrices into the Matrix Multiplier from Vivado SDK? I saw a youtube tutorial here

where he made a custom adder. He put two numbers into the register and it was able to put the output into a register 4 bytes over. I tried doing something similar to that for the mmult IP, but I didn't get anything to fall into place.

The registers can be found in xparameters.h. The register offsets can be found in the myip2x2VHDL.h file in the source folder of the design1hwwrapper.

 

 

 

 

[jpeyron]

Hi @electronicsdevices,

I haven't been able to see whats wrong with your code but here is a tutorial on making a custom IP. It also happens to be a multiplier.  Here is where the broken link should be pointing for the code. Let me know if this helps.

cheers,

Jon

[electronicsdevices]

@jpeyron

It's strange, but sometimes when I add extra things like a timer or leds, it can result in no text being printed out to the terminal if I'm trying to print to the terminal. I stripped the design down to just these and it ended up working. I'm still trying to figure out why it works sometimes but not others.

You had mentioned that 2017.1 had bugs updating hardware changes. Any links to the documentation of those bugs, or how to recreate them?

[jpeyron]

Hi @electronicsdevices,

Here is a list of Vivado 2017 known issues that Xilinx has confirmed. I will spend some more time trying to get your code based on the HDL code from here working in an IP next week. In the mean time here is our Creating a Custom IP core using the IP Integrator tutorial that might be helpful. I did find a thread dealing with matrix multiplication that is for the Zedboard( zynq processor ) that could be helpful as well here.

cheers,

Jon 

[Notarobot]

Hi @electronicsdevices

I wanted to mention that I am using Vivado 2017.1 without any issues and for this reason I think your problem is with something else.

It seems that you tested a number of projects. Sometimes these projects overlap if the project directory was not properly set up. This could create a problem.

If you are using stdin/stdout then you need to check whether UART1 was active in the Processing system configuration and the default output pins were selected. Ususally they are set by default but when you create a project from scratch. It should be mentioned that xil_prinf does not output float, use print.

UART0 can be used as well but requires reconfiguration of the BSP and extra hardware for physical interfacing. I tested it with PmodRS232.

 

 

[D@n]

@electronicsdevices,

If the code works when there's a minimum of logic, but not when there's more, and the logic that's working or not working isn't changing then ... consider your power source.  It might be that it doesn't have enough juice to keep your device powered,

Dan