Hello I have flags that I set from my PS soc. Know to read them from PL side I have an implementation error when I use the same register !

[Simo47]

Hey
I have flags that I set from my PS soc. Know to read them from PL side I have an implementation error when I use the same register !

 

    test1 <= slv_reg3(31);
    test2 <= slv_reg3(30);
    PSenable <= slv_reg3(29);

Thank you

[artvvb]

@sami47

The error "multiple driver nets" means that you are setting the same register in two different processes. Without seeing the actual code of your AXI file, it will be difficult to debug exactly why this is. So, a few questions:

What is the intended function of your AXI registers? Is their data intended to flow from PS to PL, or vice versa?

How are you setting your slave registers? When creating an AXI slave IP, the template sets them as the result of a shifting sequence, these lines of code are probably still there, and is intended to do PS to PL only. If the data is intended to flow from PL to PS, then there are a few lines of code which will need to be commented out.

To illustrate my point, the following is pseudo-code of what is probably causing your errors.

always@(posedge clk)
    my_reg <= AXI_stuff;
    
always@(posedge clk)
    other_AXI_stuff <= my_reg;
                       
always@(posedge clk)
    my_reg <= PL_stuff;

Since in this case there are two processes driving my_reg, the error that you are seeing would be created.

Hope this helps,

Arthur

[Simo47]

Thank you for your reply.
I have a bus register on 32 bit that i use it to control my data.
What I am looking for is write on the same register several times.
Else, I give PS values on this register in order to read them from PL side.

I like the Verilog but I never did it, i am working in VHDL.

I am using slv_reg3 for Control/Status

 

Thank you

 process (S_AXI_ACLK)
        variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
        begin
          if rising_edge(S_AXI_ACLK) then 
            if S_AXI_ARESETN = '0' then
              slv_reg0 <= (others => '0');
              slv_reg1 <= (others => '0');
              slv_reg2 <= (others => '0');
              slv_reg3 <= (others => '0');
            else
              loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
              if (slv_reg_wren = '1') then
                case loc_addr is
                  when b"00" =>
                    for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
                      if ( S_AXI_WSTRB(byte_index) = '1' ) then
                        -- Respective byte enables are asserted as per write strobes                   
                        -- slave registor 0
                        slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
                      end if;
                    end loop;
                  when b"01" =>
                    for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
                      if ( S_AXI_WSTRB(byte_index) = '1' ) then
                        -- Respective byte enables are asserted as per write strobes                   
                        -- slave registor 1
                        slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
                      end if;
                    end loop;
                  when b"10" =>
                    for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
                      if ( S_AXI_WSTRB(byte_index) = '1' ) then
                        -- Respective byte enables are asserted as per write strobes                   
                        -- slave registor 2
                        slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
                      end if;
                    end loop;
                  when b"11" =>
                    for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
                      if ( S_AXI_WSTRB(byte_index) = '1' ) then
                        -- Respective byte enables are asserted as per write strobes                   
                        -- slave registor 3
                        slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
                      end if;
                    end loop;
                  when others =>
                    slv_reg0 <= slv_reg0;
                    slv_reg1 <= slv_reg1;
                    slv_reg2 <= slv_reg2;
                    slv_reg3 <= slv_reg3;
                end case;
              end if;
            end if;
          end if;                   
        end process; 

 

[Notarobot]

Hi @sami47

For me your code snapshot is incomplete for making definite diagnostics. However, I am guessing that slv_reg0...3 are defined as out in your entity and your are driving them from multiple sources. That is not synthesizable code. One possible solution is to create several temporary registers and use them instead. Then you will reassign temp values to the output register in a single statement.

Another solution would be changing the architecture of your code, for example, by using Block RAM. To my knowledge DDR3/BRAM operations are faster than GPIO.

Hope you find this helpful.