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Jens

Nexys Video: LVDS via Pmod connector possible?

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Hello!

I use Nexys Video board and plan to use a Pmod connector with LVDS standard (input and output). Following the reference manual, the only Pmod connector that provides LVDS (LVDS_25) for input and outputs is JXADC (with V_ADJ=2.5V). This connector is equipped with 100 ohm series resistors. The Xilinx documentation UG471 (v1.8, pages 91-93) does not describe that series resistors are recommended or required.

Is it possible to use Pmod connector JXADC for LVDS inputs and outputs with that board? Or must I short cut the series resistors (R42-R45/R47-R50)?

Many thanks in advance!

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Posted (edited)

Hi @Jens,

The resistors along with the ESD diodes will implement a low pass filter which may limit the bandwidth. If you plan to run at frequencies >100Mhz you will most certainly need to replace those resistors with 0 ohm shunts and likely unload D7 and D8.

cheers,

Jon

Edited by jpeyron

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Just to be clear jpeyron's suggestion is for educational purposes.  Digilent does not recommended or supported modifying the board in this way.  Any modification to Digilent hardware will void the warranty and make the board ineligible for RMA.

-Kristoff

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Many thanks for your comments!

I'm also convinced that it works without the series resistors and the diodes. It is also clear that removing these elements from the board will void warranties.

However, the "Nexys Video™ FPGA Board Reference Manual" (Revised May 30, 2017) describes in Table 9 (page 20) the "Recommended usage" of the pins in question with "LVDS_25 input/output". Does this mean that Digilent supports LVDS_25 for the board without any "illegal" modifications? Or is there an official support with limited performance as @jpeyron suggests?

My limited technical understandig says that additional 2x100 ohm series resistors together with the ~4mA current of LVDS requires the LVDS outputs of the FPGA to provide additional 0.8V (to the 0.4V from the 100 ohm termination). It becomes even worse if two Nexys boards are coupled via Pmod and LVDS (additional 1.6V on output side than normal). I'm not sure if the Artix-7 can provide this relatively high differential voltage.
Xilinx DS181 (v1.22) table 11 on page 10: V_ODIFF(max) = 600mV, V_IDIFF(min) = 100mV

Jens

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Hi @Jens,

I have reached out to more experienced engineers to give input into your question. 

thank you for your patience,

Jon

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Posted (edited)

@Jens,

So, I guess that you haven't noticed any of the projects that I've submitted to the Project Vault since last October. Your question has been sort of a hobby of mine for almost a year now. The short answer is that if your PMOD IO pins are connected to an IO bank powered by 3.3V then the answer is NO. Actually, if you could rework the board with a complicated termination scheme positioned close to the IO pins the answer might be different. Vivado will complain that you are using an IOSTANDARD that is not compatible with a 3.3V IO bank; and perhaps you can ad a constraint to get past bitgen. I won't say more but you can peruse the Differential PMOD challenge Project and Fast IO project threads and files for more of what I've already said. I welcome your question. Hopefully you will get what I've never gotten.... a satisfactory response from the perpetrators of this ruse.

As to using the XADC PMOD, @jpeyron is correct about the filtering. It's true that the IO are on a 2.5V powered bank but LVDS requires 100 ohm termination between the _n and _p pins. Potentially ruining your board to get what will almost certainly be unsatisfactory results doesn't seem wise to me. You might as well use TMDS_33 and the normal differential PMOD connectors.

The shame of it is that all of this nonsense could have so easily been avoided....

Edited by zygot

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Posted (edited)

It is impossible to support all the I/O standards with the recommended terminations schemes on a generic connector. Pmod is for LVCMOS33 mainly. XADC Pmod is for analog differential mainly.

Provided that you are willing to give up warranty and do some hacking, you can try to make it work. For LVDS output you will need VCCO=2.5V which the Nexys Video is capable of. The other end will need the standard 100ohm differential termination. If you leave the two 100 ohm series resistors there, the voltage swing will be the third of the nominal value. It might be enough if the receiver has wide operating range. Short the resistors for larger swing.

For inputs, VCCO=2.5V will give you internal terminations. The series resistors will have the same effect as above. If you have only 3.3V available, you will have to load a parallel termination resistor. For the Pmod XADC on the Nexys Video you can do that on the capacitor footprint in the anti-alias filter.

All the above concerns voltage levels only. Impedance mismatches will cause considerable signal degradation if the signal edges are steep enough. Other than slowing down the signal, there is nothing more you can do.

Safe hacking!

Edited by elodg

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Posted (edited)

@elodg,

Having a dedicated analog PMOD for the XADC is a good idea. Having an 8-pin low speed LVCMOS33/LVTTL33 PMOD is a good idea. Throwing badly implemented differentially routed and pinned PMODs onto every FPGA board is a VERY BAD idea.

So what's stopping you from giving your customers a usable high speed LVDS_25 differential PMOD?

Don't hack your boards... demand what you want from your board vendor! Expect respect.

regards

Edited by zygot

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So, the phrasing is rough around the edges and with a tone of (not unwarranted) frustration, but I would like to think this is customer feedback, correct @zygot? Maybe in the future such feedback (from anybody, myself included) whether it be a wishlist, product idea, or technical recommendation, could go in the Suggestions and Feedback subsection of the Forum? I plan on posting there after this to make a few suggestions myself that D@n brought up to me (things like selection guides/tables).

As for the question, speaking as a non-layout/hardware-design engineer, I imagine that there isn't anything technical that is stopping us from creating a high speed differential port, Pmod or otherwise. Again, as a guess, I imagine right now it's the precedent of almost always making Pmod ports at 3.3 V CMOS because that is the IO Standard that Pmods have classically used for over 10 years (and Digilent sells Pmods so we support our own products). We've also only recently (on a relative scale of course) started going into the non-Academic, "trainer-style" boards that Digilent has their roots in (which I believe Clint Cole mentions in the Amp Hour podcast for anybody who happens to not have listened to it and is interested in), so I also imagine the phrase old habits die hard applies here as well to a certain extent, with relation to branching out into other uses of our boards.

Are there other things that factor all of this? Probably; it's one thing to do a production run on boards that perform in certain ways and another to sell them and without any precedent or previous 'forerunners' of our own to show appealing evidence, I imagine it's hard to get the right approval. But I'm not in those meetings, so what do I know?

If whoever is reading this has further questions or feedback, I'll be making a thread on the Suggestions and Feedback forum for just that to help make sure we do not detract away from the goal answering a user's question.

Thanks,
JColvin

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Posted (edited)

@JColvin,

At this point it's beyond frustration... now it's mostly become a challenge. The only frustration left is that a company that I've purchased a lot of product from simply refuses to acknowledge and address an issue affecting its image. This troubles me greatly.

I really do appreciate that you've been willing to respond. At least I know that there's one member of the staff who's able to say something.

There's no technical challenge.. just get the correct pins to the correct IO bank and provide signals to pin pairs. I realize that there are only so many Vadj or 2.5V IO Banks that you can have and still support the other interfaces; and there are only so many pins on those IO banks. The simple solution is that if you can't find the pins to implement an LVDS_25 interface then you shouldn't be offering a PMOD claiming to have high-speed differential signaling. At least don't sell something that isn't up to the task. User's would be much better served with a wider low speed header than 2 useless PMODS. If you have to implement a differential IO connector and you only have 3.3V IO bank pins then you could have a TMDS_33 input with the proper termination near the pins and a TMDS_33 output PMOD without terminations (each with pins connected to the global clock network). You might even be able to have adequate user selectable termination. The Genesys2 got so very close to doing this, minus the termination. At least you got global clock pins on both differential connectors; but not assigned to matching PMOD pins.... While not a first choice your users would have something worth using. Of course the best solution is to design a well thought out high speed interface for the higher cost boards.

no reasonable person expects a new spin of current board offerings. An acknowledgement of past mistakes and a correction on the next board will do suffice.  Unless making customers unhappy is corporate policy it couldn't hurt you image either.

 

Edited by zygot

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Thanks a lot for your help!

For me it looks like a weakness in the documentation of the board. "Differential" would be a better wording than "LVDS" which refers to a standard. Changing the board is a bad choice for me because I want to use the board in different student projects.

In my project we changed to the FMC connector which provides many LVDS lanes that comply with the standard. This was not my first choice because the PCB layout becomes a little more complicated and the connector is a little more costly.

Thanks again for the fruitfull discussion!

Jens

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