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Cannot see the base system design when using the tcl script xadc example from diligent website


Sam_a

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Hi, 

I am using Vivado 2017.2. I cannot see the base system design when using the tcl script GPIO/xadc examples from the diligent website (follwing instruction as given here https://www.youtube.com/watch?v=eY8-qMB0ar0).

 

It only gives me the option to create a new block design. Also, the among the GPIO/xadc examples only GPIO example works.

 

Please, can you assist.

 

Regards

Sam

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@Sam_a

Looking into it. Might not have an update until tomorrow. I have reproduced your problem in both versions, and am working on fixing it.

note: (The "tag a user" system sends a notification to that user, my username is artvvb, the person with the username arthur appears to be someone else entirely.)

Thanks,

Arthur

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@Sam_a

You may need to ask Xilinx support about simulation of the XADC IP core. The best I can do at the moment is to point you at the documentation for the core. There is a section on how to simulate it's operation, but it is a little sparse. It also appears that an AXI specific testbench is provided with the core, but I am unsure how much use this will be. You may want to look into demo code they have produced for control of the IP to see if it contains anything like that. Perhaps someone else has some experience that would help here?

Apologies,

Arthur

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hi @artvvb

 

I simulated the code and works fine. Using a static value of the Freq, does not give that error, but reading from ADC make all the signal go down to zero momentarily. Yes, you are right the division would take a considerable amount of machine cycles. But, I want to continuously monitor the ADC channels to acquire these values. I 'll try to modify the code as you have suggested and see if it removes the problem.

 

Also, is there a test bench to simulate the xADC or tutorial I can look into.

 

Thanks

Sam

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@Sam_a

Without digging in and trying to debug the code myself, I find the use of multiple if-(else if)-else statements controlling the same register in the same process potentially dangerous. I would recommend simulating the control loop and looking for unexpected results. If you aren't familiar with simulating your code, this should be a good learning experience (perhaps check out this xilinx tutorial?). First characterize what you expect your project to do with certain input patterns, then write some code to test out those assumptions and run it in the simulator - I'd recommend simulating only your control code, instead of the entire project. Alternatively, or as well, I tend to find the RTL Analysis - Open Elaborated Design - Schematic tool in Vivado to be helpful for getting an idea of how Vivado is interpreting my verilog, in block design form.

For concrete advice, narrow in on how long it takes to compute "100000 / Freq". This may be a problem, or it might not, but division is slow, and this may take multiple clock cycles to complete. A way around using division would be to pre-calculate all possible values of (100000/Freq) and store them in a look up table. There are at least three standard ways to implement this, which I can explain further if you want.

Hope this helps,

Arthur

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hi @artvvb

 

Based on the code, I am trying to use the adc channels to get information like duty ratio, frequency etc to generate PWM signal. For a brief moment, the PWM signal just vanishes. This has something to do with the how the adc values are getting read. Can you please suggest me, Is there some timing constraint? Is there something I am missing.

 

Please find the code attached.

 

Thanks

Sameer

PWM_Gen.v

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First, when I use the tcl script the xADC IP is locked so I update the IP. Once that is done then I generate the bitfile. When I load the program to the board, the code does not work.

 

Regards

Sam

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@Sam_a

This project is an HDL design, there is no block design, everything is written in Verilog and VHDL, and includes the XADC Wizard IP core.

Have you tried generating a bitstream and programming your board using the Hardware Manager? If you did and it didn't work, could you let me know what errors you saw?

Thanks,

Arthur

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