Getting weird values from XADC

[gutielo]

Hello everyone. I'm using a Zedboard and I'm running Xillinux on it. I'm getting info from the XADC using Xillybus but the values I'm getting don't seem to make sense.

I'm converting VP/VN, Vaux0P/Vaux0N and Vaux8P/Vaux8N. They're in bipolar mode. I'm just seeing what the values are without feeding them any voltage, just the noise. I'm getting values like 8200, 8A00, 7F00 and so. According to the XADC doc, only the 12 MSB contain actual information about the conversion, being the other 4 bits just for accuracy. So that'd make them 820, 8A0, 7F0... Translating that into voltages, it would be as if I was feeding it 500mV (when it's under 800h) or -500 mV (when it's over 800h). Reasonable values would start at least with a 0, like 073 for example.

At first I thought I was getting these values because I wasn't feeding it with any actual voltage source, hence the random behaviour. But then I tried following this tutorial on how to set up the XADC just using block design (without using any embedded linux) and I got the values through serial port. I modified the helloworld.c from that tutorial so I could print the hex values of the conversion (the raw data was an u32 so I just typed %xl in the printf) and values where like 0740, 0d56, and so. Removing the last 4 bits, that'd make it 074, 0d5 which I think are very reasonable values for noise.

So, should I be worried about the values I'm getting from Xillybus? Is that an expected behaviour because of the noise? Is something wrong with the way I'm using/instantiating my XADC?

UPDATE: I have tried feeding the XADC and values from Xillybus keep the same while in that demo app (the tutorial I mentioned) I'm getting them correctly so I assume this something wrong with the XADC but I can't seem to know what. Might it be the offset??

Thanks in advance!

[jpeyron]

Hi @gutielo,

Is the demo from the lab I had you use not working without the fifo and xillybus?

thank you,

Jon

[gutielo]

@jpeyron I don't know how to implement Xillybus using the demo app since it's all done with 'block design' and Xillybus is a nightmare when you open block design. So I just use a wizard to instantiate an XADC (I use DRP as interface option as opposed to AXI4Lite in the demo) and connect it to the FIFO. As I said, I'm getting values constantly but they're not correct. Is there a way I can connect the one I used in the demo? Cause that one is working right.

[jpeyron]

Hi @gutielo,

I attached a XADC HDL (verilog) project that was converted from the Nexys Video to work with Vaux8p , Vaux8n and the OLED for the Zedboard.  Use the project in the proj fold which has been modified to work with the zedboard. Hopefully this can be a starting point for you to use the xadc and xillybus without using the block design. In case you did not know this type of project programs the fpga from the hardware manager in Vivado and does not use SDK. 

cheers,

Jon

HDL_ZED_XADC.zip

[gutielo]

Hey @jpeyron Thanks for the project. Been testing it and I generated a bit file and programmed the FPGA. I only got results in Channel 1 and Channel 0 (channel 9 and 8 were always 0.000). I was wondering if there's any chance I can print those values in hex instead of decimal?

[D@n]

@gutielo,

Printing in hexadecimal sounds like a fun project!  It could be very useful to other FPGA developers using that OLED as well.

Would you be willing to do it and post your code in the project vault?

Dan

[gutielo]

I would if the project was coded in VHDL, but it's in Verilog and I'd to have to rewrite it first or learn Verilog and I don't have much time for either of the two at the moment. That's why I was asking if there was an easy way to do that in Verilog. Sorry D@n.

[D@n]

@gutielo,

Sigh.  Yeah, I can understand the perspective.  I might've had the same problem were it coded in VHDL instead of Verilog.

A shame, though.  It would've been a good and fun addition to the project Vault.

Dan

[gutielo]

@jpeyron

Hey! There's something I've noticed while running some tests. When using XADC + Xillybus, I open Hardware Manager in Vivado just to monitor the XADC. Temperature is always -273.1ºC and volts in VAUX0, VAUX8 and VP/VN is always 0.00. When I run your project, I use the Hardware Manager again to monitor and everything seems fine, temperature is at 30ºC and volts in VAUX0 looks great (even change when I put my finger on the pins, as expected). So I am starting there must be something wrong with the combo XADC + Xillybus although the XADC seems to do something, but it looks like it's always converting the same thing (although values change a little, implying is not stuck in the same result forever).

I've been trying some things with the project you uploaded. I copied the whole XADC from your project to mine and tried it with Xillybus. Got the same result as described. I'm afraid there must be something wrong in the XADC. Currently, the constraints I'm using looks like:

# XADC
set_property -dict "PACKAGE_PIN L11 IOSTANDARD LVCMOS33" [get_ports "vp_in"];
set_property -dict "PACKAGE_PIN M12 IOSTANDARD LVCMOS33" [get_ports "vn_in"];
set_property -dict "PACKAGE_PIN E16 IOSTANDARD LVCMOS33" [get_ports "vauxn0"];  # "XADC-AD0N-R"
set_property -dict "PACKAGE_PIN F16 IOSTANDARD LVCMOS33" [get_ports "vauxp0"];  # "XADC-AD0P-R"
set_property -dict "PACKAGE_PIN D17 IOSTANDARD LVCMOS33" [get_ports "vauxn8"];  # "XADC-AD8N-R"
set_property -dict "PACKAGE_PIN D16 IOSTANDARD LVCMOS33" [get_ports "vauxp8"];  # "XADC-AD8P-R"

I actually tried to do it the way you have it set up in your constraints file like:

# XADC
set_property PACKAGE_PIN L11 [get_ports "vp_in"];
set_property PACKAGE_PIN M12 [get_ports "vn_in"];
set_property PACKAGE_PIN E16 [get_ports "vauxn0"];  # "XADC-AD0N-R"
set_property PACKAGE_PIN F16 [get_ports "vauxp0"];  # "XADC-AD0P-R"
set_property PACKAGE_PIN D17 [get_ports "vauxn8"];  # "XADC-AD8N-R"
set_property PACKAGE_PIN D16 [get_ports "vauxp8"];  # "XADC-AD8P-R"

But if I did that, I got an error when generating the bitstream that said there was some sort of conflict cause PS_GPIO[0] from Xillybus was LVCMOS33 and vauxn0 was LVCMOS18 on IO Bank 35. I don't really know what this means tho.

Any clue on what might be going on? Thanks!